Wan Sik Hwang

Ultrathin graphene and graphene oxide layers as a diffusion barrier for advanced Cu metallization

We report on the diffusion barrier properties of chemical-vapor-deposition grown graphene, graphene oxide, and reduced graphene oxide (rGO) for copper metallization in integrated circuits. Single-layer graphene shows the best diffusion barrier performance among the three but it has poor integration compatibility, displaying weak adhesion and poor nucleation for Cu deposition on top of it. Within the allowable thermal budget in the back-end-of-line process, rGO in a range of 1 nm thickness shows excellent thermal stability with suitable integration compatibility at 400 °C for 30 min. The diffusion barrier property was verified through optical, physical, and chemical analyses. The use of an extremely thin rGO layer as a Cu barrier material is expected to provide an alternative route for further scaling of copper interconnect technology.

Material characteristics and equivalent circuit models of stacked graphene oxide for capacitive humidity sensors

The oxidation properties of graphene oxide (GO) are systematically correlated with their chemical sensing properties. Based on an impedance analysis, the equivalent circuit models of the capacitive sensors are established, and it is demonstrated that capacitive operations are related to the degree of oxidation. This is also confirmed by X-ray diffraction and Raman analysis. Finally, highly sensitive stacked GO sensors are shown to detect humidity in capacitive mode, which can be useful in various applications requiring low power consumption.

The Mechanism of Schottky Barrier Modulation of Tantalum Nitride/Ge Contacts

In this letter, we discuss the mechanism of Schottky barrier height (SBH) modulation of the TaN/Ge contact by varying the nitrogen concentration in the TaN. The Fermi level, which is strongly pinned near the valence band edge of Ge, moves to the conduction band edge of Ge with higher nitrogen concentration in the reactive sputtered TaN. This SBH modulation is attributed to the presence of an electric dipole induced by Ge-N bonds at the interface of the TaN/Ge contact. This SBH modulation due to the semiconductor-nitrogen bonds at the interface is not specific to TaN/Ge, but rather is a general feature in various transition-metal nitride systems on various semiconductors.

A quantitative strain analysis of a flexible single-crystalline silicon membrane

This study presents a quantitative strain analysis of a single-crystal Si membrane for high performance flexible devices. Advanced thinning and transfer methods were used to make flexible single-crystal Si devices. Two Si membrane strain gauges, each with a different stack, were fabricated on a polydimethylsiloxane/polyimide film using a silicon-on-insulator wafer. One gauge contains a 10-μm-thick handling Si layer, whereas the handling Si layer was completely removed for the other case. Although the Si membrane with the 10-μm-thick handling Si layer is flexible, the strain applied to the active Si layer (0.127%) is three times higher than the strain applied to the Si membrane without the handling Si layer (0.037%) at a bending radius of 5 mm. This leads to the more reliable electrical and mechanical performance of the device fabricated on the Si membrane without the handling Si layer. The experimental results were verified through a finite element method simulation and analytical modeling. The quantitati...

The Work Function Behavior of Aluminum-Doped Titanium Carbide Grown by Atomic Layer Deposition

The effective work function (eWF) of Al-doped titanium carbide (TiAlC) metal electrodes prepared by atomic layer deposition shows a strong dependence on the underlying gate dielectrics. The eWF of TiAlC on HfO2 shows a low value of 4.2 eV independent of the deposition temperature and process conditions, whereas that on SiO2 shifted to a midgap value of 4.7 eV, and it was sensitive to the process conditions. The mechanism underlying this TiAlC work function dependence on different gate dielectrics is investigated in detail.

Resistance analysis and device design guideline for graphene RF transistors

Graphene has attracted enormous attention in recent years because of its high carrier mobility and saturation velocity. High-performance graphene transistors for radio-frequency (RF) applications are especially attractive. Synthesis of high quality graphene sheets and application of various materials for gate dielectrics and substrates have been demonstrated. However, very few studies have been performed on the effects of graphene transistor parameters, such as parasitic resistances and graphene quality, in relation to RF applications. Here we report a systematic study of those effects on electrical performance depending on the transistor structure. It is found that the access resistance and contact resistance are the dominant factors leading to degradation of the device performance, especially in deep scaled devices. A guideline for device structural parameter design for required RF performance is discussed. Furthermore, we demonstrate that the newly proposed self-aligned structure can minimize access resistance component, resulting in 6 times higher cut-off frequency compared to that of the conventional structure, when the gate length is 50 nm. The findings of this study can be used to predict the device RF performance and thus help the design of graphene transistor structures to meet specific requirements.

Vertically Formed Graphene Stripe for 3D Field-Effect Transistor Applications

A 100-nm wide, vertically formed graphene stripe (GS) is demonstrated for three-dimensional (3D) electronic applications. The GS forms along the sidewall of a thin nickel film. It is possible to further scale down the GS width by engineering the deposited thickness of the atomic layer deposition (ALD) Ni film. Unlike a conventional GS or graphene nanoribbon (GNR), the vertically formed GS is made without a graphene transfer and etching process. The process integration of the proposed GS FETs resembles that of currently commercialized vertical NAND flash memory with a design rule of less than 20 nm, implying practical usage of this formed GS for 3D advanced FET applications.

The Impact of an Ultrathin Y 2 O 3 Layer on GeO 2 Passivation in Ge MOS Gate Stacks

This paper investigates the impact of an atomic layer-deposited Y₂O₃ dielectric on the passivation of a GeO₂ layer in GeO₂-based Ge gate stacks. The equivalent oxide thickness scalability and thermal stability of the ultrathin Y₂O₃ layer are evaluated at different Y₂O₃ thicknesses and annealing conditions in detail. Experimental results show that a Y₂O₃ layer thickness of 1.0 nm is required to serve as a GeO₂ passivation layer while retaining gate-stack performance at 400 °C postdeposition annealing. However, at a higher annealing temperature of 500 °C, the barrier property deteriorates and allows GeO desorption. The proposed gate-stack implies the applicability of a Y₂O₃ passivation method for further scaled GeO₂-based Ge gate stacks.

Very Low-Work-Function ALD-Erbium Carbide (ErC 2 ) Metal Electrode on High-

Erbium carbide (ErC2) prepared by atomic layer deposition (ALD) is successfully demonstrated for the first time as a novel work function (WF) metal for nMOSFET applications. The prepared ErC2 shows a very low effective WF (eWF), as low as 3.9 eV on HfO2, yet with excellent thermal stability. In addition, it did not show significant Fermi-level pinning on high-k dielectrics even after high-temperature annealing. The low eWF property of ErC2 originates from the properties of the lanthanide family, while its good thermal stability is attributed to the properties of metal carbides. ALD-ErC2 has superior conformality over other deposition methods, and thus is a strong candidate for 3-D structure devices.

K

We demonstrated that reduced graphene oxide (rGO) can suppress electromigration (EM) of Cu interconnect lines. This improvement in the EM lifetime is attributed to the presence of functional groups between the rGO and Cu atoms. Further enhancement of the EM lifetime was achieved by increasing the functionality of graphene by mixing graphene oxide (GO) with polyvinylpyrrolidone (PVP). It is revealed that the dominant EM path of Cu is successfully changed from the surface to grain boundaries by the use of an ultrathin (2.5 nm) PVP/GO capping layer.