Jai-Kwang Shin

Effects of TMAH Treatment on Device Performance of Normally Off

Normally off Al2O3/GaN MOSFETs are fabricated by utilizing a simple tetramethylammonium hydroxide (TMAH) treatment as a postgate-recess process. The TMAH-treated device with a gate length of 2.5 μm exhibited excellent device performances, such as a threshold voltage of 3.5 V, a maximum drain current of 336 mA/mm, and a breakdown voltage of 725 V, along with extremely small gate leakage current of about 10-9 A/mm at Vgs = 15 V, which is approximately six orders lower in magnitude compared to that of the device without TMAH treatment.

\hbox{Al}_{2}\hbox{O}_{3}/\hbox{GaN}

The impact of gate metals on the threshold voltage (VTH) and the gate current of p-GaN gate high-electron-mobility transistors (HEMTs) is investigated by fabricating p-GaN gate HEMTs with different work function gate metals-Ni and W. p-GaN gate HEMTs incorporate a p-GaN layer under the gate electrode as the gate stack on top of the AlGaN/GaN layer. In comparison to the Ni-gate p-GaN HEMTs, the W-gate p-GaN HEMTs showed a higher VTH of 3.0 V and a lower gate current of 0.02 mA/mm at a gate bias of 10 V. Based on TCAD device simulations, we revealed that these high VTH and low gate current are attributed to the low gate metal work function and the high Schottky barrier between the p-GaN and the W gate metal.

MOSFET

Scanning tunneling microscopy (STM) and density functional theory (DFT) calculations were used to investigate the surface morphology and electronic structure of graphene synthesized on Cu by low temperature chemical vapor deposition (CVD). Periodic line patterns originating from the arrangements of carbon atoms on the Cu surface passivate the interaction between metal substrate and graphene, resulting in flawless inherent graphene band structure in pristine graphene/Cu. The effective elimination of metal surface states by the passivation is expected to contribute to the growth of monolayer graphene on Cu, which yields highly enhanced uniformity on the wafer scale, making progress toward the commercial application of graphene.

p-GaN Gate HEMTs With Tungsten Gate Metal for High Threshold Voltage and Low Gate Current

We investigate peculiar dopant deactivation behaviors of Si nanostrucures with first principle calculations and reveal that surface dangling bonds (SDBs) on Si nanostructures could be fundamental obstacles in nanoscale doping. In contrast to bulk Si, as the size of Si becomes smaller, SDBs on Si nanostructures prefer to be charged and asymmetrically deactivate n- and p-type doping. The asymmetric dopant deactivation in Si nanostructures is ascribed to the preference for negatively charged SDBs as a result of a larger quantum confinement effect on the conduction band. On the basis of our results, we show that the control of the growth direction of silicon nanowire as well as surface passivation is very important in preventing dopant deactivation.

Passivation of Metal Surface States: Microscopic Origin for Uniform Monolayer Graphene by Low Temperature Chemical Vapor Deposition

We investigated low-frequency noise (LFN) characteristics in passivated InZnO thin-film transistors with various active layer thicknesses. These LFNs are matched to the mobility fluctuation model [F. N. Hooge, IEEE Trans. Electron Devices 41, 1926 (1994)]. According to this model, the Hooge’s parameter (αH) is significantly increased as the active layer thickness is decreased. By plotting the αH with the effective mobility (μeff), we found that the αH is proportional to the μeff−1. This indicates that the mobility fluctuation by the impurity scattering is significantly increased as the active layer thickness is decreased, and that is the main origin of the LFN increments in the thinner active-layer-thickness devices.

Asymmetric Doping in Silicon Nanostructures: The Impact of Surface Dangling Bonds

Using first-principles calculations of graphene having high-symmetry distortion or defects, we investigate band gap opening by chiral symmetry breaking, or intervalley mixing, in graphene and show an intuitive picture of understanding the gap opening in terms of local bonding and antibonding hybridizations. We identify that the gap opening by chiral symmetry breaking in honeycomb lattices is an ideal two-dimensional (2D) extension of the Peierls metal-insulator transition in 1D linear lattices. We show that the spontaneous Kekule distortion, a 2D version of the Peierls distortion, takes place in biaxially strained graphene, leading to structural failure. We also show that the gap opening in graphene antidots and armchair nanoribbons, which has been usually attributed to quantum confinement effects, can be understood with the chiral symmetry breaking.

The impact of active layer thickness on low-frequency noise characteristics in InZnO thin-film transistors with high mobility

We measured Radio-Frequency (RF) performance of devices with graphene grown using low temperature Inductively-Coupled Plasma Chemical Vapor Deposition (ICP-CVD) method on 6-inch wafer for the first time. To remove the coupling of electrode in-plane, we introduced locally-embedded-back-gate using TiN metal. The symmetric structure of 2-gate fingers was adopted to reduce misalign issue during fabrication of the structure with underlap between Gate and Source/Drain, which was also adopted for the reduction of parasitic capacitance due to gate oxide with high dielectric constant. Cutoff frequency (ƒT) increase is moderately obtained with the decrease of gate length. Despite the low gm due to underlap region, we obtained ƒT =80 GHz.

Band gap opening by two-dimensional manifestation of peierls instability in graphene.

Micro villus patterning (MVP) technology which delivers the maximized cell capacitance is discussed. The key feature of the MVP technology is the formation of a hemispherical grain (HSG) archipelago and its transference to the underlayered oxide. The HSG archipelago pattern is produced on the oxide layer, and, by using that pattern as an etch mask, the oxide archipelago pattern is again transferred to the storage poly for the formation of villus bars by anisotropic dry etch. After the etching process, the oxide etch mask pattern is stripped away by using oxide wet etchant, so that additional Fin undercut structure is achieved underneath the main body. The main body of the storage electrode can be formed by single deposition and etch process, so that the storage electrode structure is strong enough to maintain its physical stability in spite of the complication of its shape. A 256-Mb DRAM-cell size of 0.6 approximately 0.8 mu m/sup 2/ having more than 30 fF of cell capacitance with a stack structure, has been realized.<<ETX>>

RF performance of pre-patterned locally-embedded-back-gate graphene device

The integration of electronically active oxide transistors onto silicon circuits represents an innovative approach to improving the performance of devices. In this paper, we present high performance oxide transistor for use as gate drive circuitry integrated on top of a power electronic device, providing a novel power system. Specifically, as a core device component in gate driver, oxide transistor exhibits remarkable performance such as, high mobility (23~47cm2/Vs) and high breakdown voltage (BV) of 60~340V despite low process temperatures (<;300°C). In addition, we demonstrate the dynamic behavior of the inverter and the latch produced by oxide transistor and thus a complete and functioning gate drive circuitry can be implemented on top of power management integrated circuit (PMIC) as depicted in the report.

Micro villus patterning (MVP) technology for 256 Mb DRAM stack cell

Traps and trap-related effects in recessed-gate normally-off AlGaN/GaN-based MOSHEMT with SiO2 gate dielectric were characterized. Hysteresis in ID-VG was observed at elevated temperature (~120°C) due to the traps. To understand the traps, current transient in drain was investigated at given gate and drain pulses with different temperatures. Two groups of time constants were extracted: one is nearly constant and the other is decreased with temperature. Extracted activation energies from the drain current transients with temperature are 0.66 eV and 0.73 eV, respectively, for given gate and drain pulses. Using extracted exponential trap density profile from frequency dependent conductance method [4], we could understand C-V behavior with frequency. It was shown that traps inside AlGaN layer are a main cause for the decrease of capacitance at high frequency in inversion region. The pulsed I-V characteristics also show frequency dependence.