Won-Young Jung

A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips

A novel high-speed and low-voltage CMOS level shifter circuit is proposed. The proposed circuit is suitable for block-level dynamic voltage and frequency scaling (DVFS) environment or multiple-clock and multiple-power-domain logic blocks. In order to achieve high performance in a chip consisting of logic blocks having different VDD voltages, the proposed circuit uses the circuit techniques to reduce the capacitive loading of input signals and to minimize the contention between pull-up and pull-down transistors through positive feedback loop. The techniques improve the slew rate of output signals, so that the level transient delay and duty distortions can be reduced. The proposed level up/down shifters are designed to operate over a wide range of voltage and frequency and verified with Berkeleys 65 nm CMOS model parameters, which can cover a voltage range from 0.6 to 1.6V and at least frequency range up to 1000 MHz within 3% duty errors. Through simulation with Berkeleys 65 nm CMOS model parameters, the level shifter circuits can solve the duty distortion preventing them from high speed operation within the duty ratio error of 3% at 1 GHz. For verification through performance comparison with reported level shifts, the simulations are carried out with 0.35 μm CMOS technology, 0.13 μm IBM CMOS technology and Berkeleys 65 nm CMOS model parameters. The compared results show that delay time and duty ratio distortion are improved about 68% and 75%, respectively.

P-type isolated GGNMOS with a deep current path for ESD protection

In this paper, we propose a P-type Isolated GGNMOS (PI-GGNMOS) with a deep current path to improve holding voltage (Vh) of Electro-Static Discharge (ESD) protection device. In order to make the deep current path under the channel, the proposed ESD protection device has a p-type stud between source and the channel, compared to the conventional GGNMOS (Gate-Grounded NMOS). To verify the performance of the proposed structure, we simulated and measured the test structure that is fabricated in a 0.35μm Bipolar-CMOS-DMOS (BCD) process. We found that the proposed structure improves the holding voltage from 6.4V to 8.48V for 5V GGNMOS at 5.3μm pitch. In case of conventional 7V GGNMOS at 7.0μm pitch, the holding voltage is 8.7V. Therefore, we can use 5V PI-GGNMOS as a 7V ESD protection device with 32 % pitch reduction compared to conventional 7V ESD device without any additional process. The actual size of ESD cell is saved by 42.3%, considering It2. This improvement is attributed to the p-type stud which reduces gain and extends effective base width of parasitic NPN in GGNMOS. Consequently, the PI-GGNMOS can apply for upper range ESD protection at same cost.

Low-Capacitance Low-Voltage Triggered SCR ESD Clamp Using nMOS With Asymmetric Drain for RF ICs

A novel low-capacitance low-voltage triggered silicon-controlled rectifier (LC-LVTSCR) electrostatic discharge (ESD) clamp is proposed in a 0.13-μm RF process. The proposed ESD clamp meets the ESD robustness and the RF requirement. The mechanism of the proposed LC-LVTSCR is investigated by T-CAD simulations, and a method to reduce the parasitic capacitance is presented. From the measurement, it was observed that the proposed ESD clamp has approximately 50% lower parasitic capacitance compared to the conventional LVTSCR device. The proposed ESD clamp was successfully used in a 2.4-GHz RF transceiver chip. The RF chip with the new proposed LC-LVTSCR passed a human body model 1-kV and machine model 100-V ESD test.

PLL Jitter Analysis with Various Power Delivery Networks on a Board

Increasing frequency and reducing time margin have made desigen of power delivery neworks (PDNs) on board to be an integral part of chip designs. Power delivery network designs are usually achieved by mounting the decoupling capacitors on power plates so that the designed power impedance is relatively lower on the interested frequency ranges. But, some parts out of frequency-dependant impedance profile of power delivery networks that make the major effect on noise performances of digital, RF, and analog chips does not be very clear according to chips family. In this paper, we demonstrate the analysis of power delivery networks for the multiple voltage domains on an analog PLL jitter performance. We look for self impedances of chip mounted on board according to decoupling capacitors size, their positions, and DC-DC chip. We analyze the PLLs jitter characteristics depending on self-impedance profiles for core and IO circuit. Through this work, it is clear that the PDNs design concept which is considering inherent operation characteristics should be adapted for the efficient and costive system.

Novel Method of Interconnect Worstcase Establishment with Statistically-Based Approaches

In order for the interconnect effects due to process-induced variations to be applied to the designs in 0.13 μm and below, it is necessary to determine and characterize the realistic interconnect worstcase models with high accuracy and speed. This paper proposes new statistically-based approaches to the characterization of realistic interconnect worstcase models which take into account process-induced variations. The Effective Common Geometry (ECG) and Accumulated Maximum Probability (AMP) algorithms have been developed and implemented into the new statistical interconnect worstcase design environment. To verify this statistical interconnect worstcase design environment, the 31-stage ring oscillators are fabricated and measured with UMC 0.13 μm Logic process. The 15-stage ring oscillators are fabricated and measured with 0.18 μm standard CMOS process for investigating its flexibility in other technologies. The results show that the relative errors of the new method are less than 1.00%, which is two times more accurate than the conventional worstcase method. Furthermore, the new interconnect worstcase design environment improves optimization speed by 29.61–32.01% compared to that of the conventional worstcase optimization. The new statistical interconnect worstcase design environment accurately predicts the worstcase and bestcase corners of non-normal distribution where conventional methods cannot do well.

Fast and Accurate Power Bus Designer for Multi-Layers High-Speed Digital Boards

Fast and accurate power bus designer (FAPUD) for multi-layers high-speed digital boards is the power supply network design tool for accurate and precise high speed board. FAPUD is constructed based on two main algorithms of the PBEC (Path Based Equivalent Circuit) model and the network synthesis method. The PBEC model exploits simple arithmetic expressions of the lumped 1-D circuit model from the electrical parameters of a 2-D power distribution network. The circuit level design based on PBEC is carried with the proposed regional approach. The circuit level design directly calculates and determines the size of on-chip decoupling capacitors, the size and the location of off-chip decoupling capacitors, and the effective inductances of the package power bus. As a design output, a lumped circuit model and a pre-layout of the power bus including a whole decoupling capacitors are obtained after processing FAPUD. In the tuning procedure, the board re-optimization considering simultaneous switching noise (SSN) added by I/O switching in can be carried out because the I/O switching effect on a power supply noise can estimate for the operation frequency range with the lumped circuit model. Furthermore, if a design changes or needs to be tuned, FAPUD can modify design by replacing decoupling capacitors without consuming other design resources. Finally, FAPUD is accurate compared with conventional PEEC-based design tools, and its design time is 10 times faster than that of conventional PEEC-based design tools.

Improvement method of the machine-model ESD robustness for a smart power IC

The failure behavior of the Smart Power IC using a 0.35 μm Bipolar-CMOS-DMOS was investigated, and the major ESD failure spots were found at the corner of the guard-ring structure and the high-voltage transistor, which is connected between the different power domains (Vdd-Vcc). The mechanism of these failures is investigated by the T-CAD simulation, and the method to improve the Machine Model (MM) Robustness is provided. To improve the MM level, the power rail was modified for blocking an unexpected ESD current path using the cost-effective metal revision. This increased MM ESD robustness significantly from 150V to 230V.

A new robust capacitance mis-match measurement for analog/mixed-signal applications

This paper presents a new capacitance mis-match measurement method which is more accurate and robust compared to the conventional FGCM method. The resolution of the FGCM method is limited by the parasitics and equipments. In the proposed method, instead of the source node, the voltage on the capacitance is considered as a reference in measurement in order to minimize the effects of pre-existing charge in the floating gate and confirm that the MOSFET is operating in the saturation region. Results of 2-D process and device simulation and the measured data in a 0.13 µm process are compared to verify the proposed method. It shows that, compared to the ideal value, the average of the new method are within 0.15% compared to 23.9% in conventional method while the standard deviation is within 0.2%. Also, this method can be easily implemented because the measurement method of Sr and Sm are identical to the conventional method. As a result, using the proposed method, the MIM capacitance can be measured at a much higher resolution than using the conventional method, i.e. to a sub-femto level.

Statistical worstcase interconnect modeling based on non-normal distributed process variations for nanometer era

In this paper, we propose a new statistically-based approach for the characterization of the realistic worstcase interconnect models. In order to extract optimized parameters consistently in the worstcase simulation and to solve the non-normal distribution problems that were treated as normal distributions in the previous methods, the effective common geometry (ECG) and accumulated maximum probability (AMP) algorithms have been developed and implemented into the new statistical worstcase interconnect design environment. The delay time of the 31-stage ring oscillator that is manufactured in UMC 0.13 mum logic and 15-stage ring oscillator in 0.18 mum standard CMOS process was measured. When the algorithms were used to determine the worstcase, it was two times more accurate with the relative error less than 1.00% than that of the conventional Monte Carlo method (MCM). The new worstcase interconnect design environment improved the optimization speed by 32.01% compared to that of the conventional worstcase optimizer. The new worstcase interconnect design environment fast and accurately predicted the worstcase/bestcase of the non-normal distribution which conventional methods cannot do very well.