Ji-Hoon Lim

A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips

A novel high-speed and low-voltage CMOS level shifter circuit is proposed. The proposed circuit is suitable for block-level dynamic voltage and frequency scaling (DVFS) environment or multiple-clock and multiple-power-domain logic blocks. In order to achieve high performance in a chip consisting of logic blocks having different VDD voltages, the proposed circuit uses the circuit techniques to reduce the capacitive loading of input signals and to minimize the contention between pull-up and pull-down transistors through positive feedback loop. The techniques improve the slew rate of output signals, so that the level transient delay and duty distortions can be reduced. The proposed level up/down shifters are designed to operate over a wide range of voltage and frequency and verified with Berkeleys 65 nm CMOS model parameters, which can cover a voltage range from 0.6 to 1.6V and at least frequency range up to 1000 MHz within 3% duty errors. Through simulation with Berkeleys 65 nm CMOS model parameters, the level shifter circuits can solve the duty distortion preventing them from high speed operation within the duty ratio error of 3% at 1 GHz. For verification through performance comparison with reported level shifts, the simulations are carried out with 0.35 μm CMOS technology, 0.13 μm IBM CMOS technology and Berkeleys 65 nm CMOS model parameters. The compared results show that delay time and duty ratio distortion are improved about 68% and 75%, respectively.

One-chip multi-output SMPS using a shared digital controller and a pseudo relaxation oscillating technique

This paper suggests a multi-level and multi-output SMPS based on a shared digital logic controller through separately operating in exclusive time period. The number of output voltages and their levels can be programmably selected for multiple power voltages. The proposed SMPS also shows a novel DPWM generator based on Pseudo Relaxation Oscillating technique. Although the shared architecture can be devised with small area and high efficiency, it has critical drawbacks that real-time control of each DPWM generators are impossible and its output voltage can be unstable. To solve these problems, a real-time current compensation scheme is proposed as a solution. A current consumption of the core block and entire block with four driver buffers was simulated about 4.9mA and 30mA at 10MHz switching frequency and 100MHz core operating frequency. Output voltage ripple is 11 mV at 3.3V output voltage. Over/undershoot voltage was HmV/19mV at 3.3V output voltage. The noise performance was simulated at 800mA @100KHz load regulation. Core circuit can be implemented small size in 700 μm × 800 μm area. For the verification of proposed circuit, the simulations were carried out with Dong-bu Hitek BCD 0.35μm technology.

A SEAMLESS-CONTROLLED DIGITAL PLL USING DUAL LOOPS FOR HIGH SPEED SOCS

A new dual-loop digital phased-locked loop (DPLL) architecture is presented. This novel architecture is designed to provide a wide operating frequency range, high precision, and small jitter, and fits over a relatively small area. To achieve these characteristics, the architecture is implemented using a coarse loop with an UP/DOWN counter and a coarse digital-to-analog converter (DAC) to rapidly reduce the phase error, and a fine loop with a time-to-digital converter (TDC) and a fine DAC to provide more precision. Furthermore, the seamless-frequency tracking architecture based on a code conversion between the coarse cell and the fine cell of the DAC is devised to improve the lock-in stability. The chip is fabricated with Dongbu HiTek 0.18-μm CMOS technology. It has a wide operation range of 0.4–1.4 GHz, and an area of 0.195 mm2. The measured results show 15.64 ps peak-to-peak jitter and 2.22 ps rms jitter, and a power dissipation of 16.2 mW at 1 GHz.

PLL Jitter Analysis with Various Power Delivery Networks on a Board

Increasing frequency and reducing time margin have made desigen of power delivery neworks (PDNs) on board to be an integral part of chip designs. Power delivery network designs are usually achieved by mounting the decoupling capacitors on power plates so that the designed power impedance is relatively lower on the interested frequency ranges. But, some parts out of frequency-dependant impedance profile of power delivery networks that make the major effect on noise performances of digital, RF, and analog chips does not be very clear according to chips family. In this paper, we demonstrate the analysis of power delivery networks for the multiple voltage domains on an analog PLL jitter performance. We look for self impedances of chip mounted on board according to decoupling capacitors size, their positions, and DC-DC chip. We analyze the PLLs jitter characteristics depending on self-impedance profiles for core and IO circuit. Through this work, it is clear that the PDNs design concept which is considering inherent operation characteristics should be adapted for the efficient and costive system.

Spectrum analysis of switched-capacitor mode DPWM generator with Spread-Spectrum Clocking circuit

In this paper, we analyzed a spectrum of the SMPS (Switching Mode Power Supply) which uses DPWM (Digital Pulse Width Modulation) and adopts SSC (Spread Spectrum Clocking) circuit to reduce EMI (Electro-Magnetic Interference) noise. Generally, SSC circuits are used in order to reduce noise peaks by spreading switching frequency spectrum. Such noise peak reduction is verified with a general FFT (Fast Fourier Transform) method through sufficiently long time which includes many switching cycles. However, effects of drastic changes of power supply voltage such as voltage dropping, onetime noise or bounce in power distribution network are apparently not revealed in the spectrum because their effects are averaged down in the general FFT method. These ripples in power distribution become sources of EMI failures. For accurate spectrum analysis in the transition period, FFT should be performed separately with respect to each transient section. Therefore, we carried out short-time Fourier transform (STFT) with respect to several local window sections as well as general Fourier transform with respect to the overall interval. The separated local windows are the overshoot section and the undershoot section.