Choong-ho Lee

Novel body tied FinFET cell array transistor DRAM with negative word line operation for sub 60nm technology and beyond

In this paper, a highly manufacturable 512M FinFET DRAM with novel body tied FinFET cell array transistor on bulk Si substrate has been successfully integrated and the characteristics were compared with RCAT (Recess Channel Array Transistor) and planar cell array transistor DRAM for the first time. We also propose the NWL (Negative Word Line) scheme with low channel doping body tied FinFET for a highly manufacturable FinFET DRAM for sub 60nm technology node.

A study of negative-bias temperature instability of SOI and body-tied FinFETs

Negative-bias temperature-instability (NBTI) characteristics are carefully studied on SOI and body-tied pMOS FinFETs for the first time. It was observed that a narrow fin width degraded device lifetime more than a wider fin width. Electrons generated by the NBT stress are accumulated at the center of a silicon fin and cause energy-band bending. This results in an incremental hole population at the interface. The energy band is bent more steeply at the narrow fin than at the wide fin by the accumulated electrons. A body-tied FinFET shows better immunity to NBT stress due to a substrate contact.

Paired FinFET Charge Trap Flash Memory for Vertical High Density Storage

A new type of memory, paired FinFET charge trap memory is reported. It consists of two split silicon fins and insulator between them. Two channels are formed on the outer surface of silicon so doubled integration density can be achieved. We successfully fabricated paired FinFET SONOS devices. It shows good program and erase characteristics. Independent programming on each storage nodes is demonstrated. The circuit configuration for NAND flash application is also proposed

Fully integrated SONOS flash memory cell array with BT (body tied)-FinFET structure

Fully integrated SONOS memory cell arrays with BT (body tied)-FinFET structure have been fabricated successfully by using manufacturable NOR flash technology. The uniformity of threshold voltage (V/sub th/) distribution of the fabricated FinFET SONOS cells is fairly better than that of conventional flash cells thanks to both the widening effective channel width of FinFET structure and negligible coupling interference of SONOS device. New two-step channel implantation process has been introduced for the compensation for the boron out-diffusion of a three-dimensional silicon fin structure. The measured FinFET SONOS cells with a two-step channel doping profile show the improved program and erase characteristics. For the improvement of program/erase and retention characteristics all together, we have investigated the modulation of erase bias condition with respect to back tunneling effect.

SONOS-Type FinFET Device Using P+ Poly-Si Gate and High-k Blocking Dielectric Integrated on Cell Array and GSL/SSL for Multi-Gigabit NAND Flash Memory

For the multi-gigabit NAND flash memory, SONOS-type FinFET device with p+ gate and high-k blocking dielectric has been integrated both on the cell array and GSL/SSL for the first time. The advantages of the FinFET structure for the NAND flash application have been theoretically and experimentally demonstrated, and the results show that the 85 % improved on-cell current is achievable using FinFET device. The enhanced programming and retention characteristics of FinFET have been also presented, and modeled by the potential changes on fully-depleted body of the sub-40 nm ultra-narrow fin

Trap Layer Engineered FinFET NAND Flash with Enhanced Memory Window

This paper presents the trap layer engineered body-tied FinFET device for MLC NAND flash application. The device design parameters for high density NAND flash memory have been considered, and the advantages of FinFET structure and high-k blocking dielectric in such device have been demonstrated. Based on the WN nano-dot memory device, the trap layer engineering using nitride layer has been performed, and the results show that the memory window is improved from 2.6 V to 7.8 V by utilizing engineered trap layer at 14 MV/cm F-N programming, and it is proposed as a possible MLC NAND device structure

Channel length independent subthreshold characteristics in submicron MOSFETs

This work reports an anomalous subthreshold characteristic of the MOSFET for the first time. It is observed that the subthreshold characteristic does not change as the channel length decreases. The cause of channel length independent subthreshold characteristics is identified as the localized pileup of channel dopants near the source and drain ends of the channel. The low surface potential of this pileup region limits the subthreshold current of MOSFET. As a result, the ratio of on-current to off-current for this MOSFET increases as the channel length is reduced, which is an important parameter for low-voltage operation. It is found that a MOSFET with channel length independent subthreshold characteristic is more suitable for low-voltage operation.

Parasitic S/D resistance effects on hot-carrier reliability in body-tied FinFETs

Hot-carrier effects (HCEs) in fully depleted body-tied FinFETs were investigated by measuring the impact-ionization current. To understand the hot-carrier degradation mechanism, stress damages were characterized by dc hot-carrier stress measurement for various stress conditions and fin widths. The measurement results show that the generation of interface states is a more dominant degradation mechanism than oxide-trapped charges for FinFETs with a gate-oxide thickness of 1.7 nm. It was found that a parasitic voltage drop due to a significant source/drain extension resistance plays an important role in suppressing the HCEs at narrow fin widths. This letter can provide insight determining the worst stress condition for estimating the lifetime and optimizing between reliability and ON-state drain-currents.

A highly manufacturable integration technology for 27nm 2 and 3bit/cell NAND flash memory

A highly manufacturable multi-level NAND flash memory with a 27nm design rule has been successfully developed for the first time. Its unit cell size is 0.00375um2 (with overhead). Self Aligned Reverse Patterning is used to improve initial Vth distribution induced from DPT (Double Patterning Technology) process. By using advanced channel doping technique, the channel junction leakage is minimized and the Vpass window is improved. The optimized doping structure and cell operation scheme are evaluated. And finally 2 and 3bit per cell operation are successfully demonstrated with flash cells of 32Gb density with reasonable reliability.

Body effects in tri-gate bulk FinFETs for DTMOS

Body factor was investigated in tri-gate bulk FinFET for the first time. Increment of on-state current and decrement of off-state current are achieved by body bias modulation. Electrical measurements were carried out to investigate the body effects in view points of a fin width that governs short-channel effects. A wide fin width was preferable for a dynamic threshold voltage operation and wide range of the threshold adjustment, however, the fin width is limited for suppression of short-channel effects. This work can provide feasibility of DTMOS application of FinFETs for low-power and high-performance application