Seong-Goo Kim

A New Capacitorless 1T DRAM Cell: Surrounding Gate MOSFET With Vertical Channel (SGVC Cell)

We propose a surrounding gate MOSFET with vertical channel (SGVC cell) as a 1T DRAM cell. To confirm the memory operation of the SGVC cell, we simulated its memory effect and fabricated the highly scalable SGVC cell. According to simulation and measurement results, the SGVC cell can operate as a 1T DRAM having a sufficiently large sensing margin. Also, due to its vertical channel structure and common source architecture, it can readily be made into a 4F2 cell array

A Novel Low Leakage Current VPT(Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology

for 4F2 DRAM Cell Array with sub 40 nm Technology Jae-Man Yoon, Kangyoon Lee, Seung-Bae Park, Seong-Goo Kim, Hyoung-Won Seo, Young-Woong Son, Bong-Soo Kim, Hyun-Woo Chung, Choong-Ho Lee*, Won-Sok Lee* *, Dong-Chan Kim* * *, Donggun Park*, Wonshik Lee and Byung-Il Ryu ATD Team, Device Research Team*, CAEP*, PD Team***, Semiconductor R&D Division, Samsung Electronics Co., San #24, Nongseo-Dong, Kiheung-Gu, Yongin-City, Kyunggi-Do, 449-711, Korea Tel) 82-31-209-4741, Fax) 82-31-209-3274, E-mail)

Robust Metal/AHO/HSG-Cylinder Capacitor Technology Using Diagonal Cell Array Scheme and Double Mold Oxide

In this paper the novel robust Hemispherical Grain (HSG)-merged Al2O3/HfO2 (AHO) capacitor with diagonal cell array scheme and double mold oxide (DMO) is introduced. The capacitor process with diagonal cell array scheme and double mold oxide can maximize storage node (SN) height up to 2.0 µm in 0.11 µm dynamic random access memory (DRAM) technology by enlarging the bottom size of SN. Also we developed the HSG-merged AHO capacitor for the first time in mass production. The HSG-merged AHO capacitor technique exhibited a capacitance enhancement by 24% without any significant decrease in breakdown voltage compared to Al2O3 (ALO) capacitor.

Memory cell capacitor using cross double patterning technology for gigabit density DRAM

In order to achieve dynamic random access memory (DRAM) with high density and high performance, abrupt scaling down of memory device is necessary. But lithography tool cannot follow up memory device scaling down. Double patterning technology (DPT) has been reported as a promising candidate to extend lithography limit [1, 2]. But DPT has a technical problem of pattern to pattern overlay [3]. To overcome overlay problems, cross double patterning technology (cross DPT) in which second pattern is perpendicular to first one is introduced. In this paper, for the first time, memory cell capacitor using cross DPT is successfully developed. Process integration and electrical characteristics of memory cell capacitor using cross DPT is presented.

Improved Electrical Characteristics and Retention Time of DRAMs Using HSG-merged-AHO Cylinder Capacitor

Fully integrated 512Mb DRAMs using HSG-merged-AHO cylinder capacitor were successfully developed for the first time. Improved electrical characteristics and retention time of HSG-merged-AHO capacitor DRAM was achieved without any capacitor-related leakage current failure in 110nm technology. This technology is expected to be extended to sub-100nm technology