Jae-soon Lim

A robust alternative for the DRAM capacitor of 50 nm generation

As a new alternative for the DRAM capacitor of 50 nm generation, Ru/Insulator/TiN (RIT) capacitor with the lowest Toxeq of 0.85 nm has been successfully developed for the first time. TiO/sub 2//HfO/sub 2/ and Ta/sub 2/O/sub 5//HfO/sub 2/ double-layers were used as dielectric materials. After full integration into 512 Mbits DRAM device, the RIT capacitor showed good electrical properties and thermal stability up to 550/spl deg/C and its time-dependent-dielectric-breakdown behavior sufficiently satisfied 10-year lifetime within a DRAM operation voltage.

Evaluation of Novel Sr Precursors for Atomic Layer Deposition of SrO Thin Film

Atomic layer deposition (ALD) process to deposit SrO film using novel Sr precursor – Sr (Methoxy-TetramethylHeptadiene)2 was estimated. Fig.1 showed the chemical structure of the synthesized Sr(MTHD)2. Fig. 2 showed thermal gravimetric analysis results of Sr(MTHD)2 and commercially used Sr (Tetra-Methyl Hetadiene)2. 50 % precursor evaporation temperature (T50) of Sr (MTHD)2 was 330 C, which was 30 C lower than that of Sr(TMHD)2. Liquid delivery system with flash evaporator was used to transport the precursors to substrate. The precursors were dissolved in Tetra Hydro Furan (THF) to prevent clogging during the delivery process. Ozone was used as a reactant to deposit SrO. It was found that thickness uniformity range of SrO film on Si wafer was less than 2 %. The deposition rate of SrO film using new Sr precursor was 0.4 A/cycle, which was almost same regardless of substrate temperatures up to 400 C. High vapor pressure and good thermal stability of new Sr precursor make it promising candidates for ALD precursors to deposit SrTiO3, aSrTiO3. Fig.1. Chemical structure of Sr(MTHD)2

Evaluation of ALD grown strontium-doped HfO 2 thin films as capacitor dielectric for 40nm DRAM Device and beyond

Introduction As the innovative scale-down of DRAM device continues, 40nm generation becomes close at hand. To satisfy the cell capacitance of 25fF in 40nm design rule, the equivalent oxide thickness (EOT) of a dielectric material should be as low as 0.5nm. TiN/insulator/TiN(TIT) capacitor using HfO2 has been successfully developed for 70nm generation.[1] Therefore the scale-down of DRAM device has required new high-k dielectric and electrode. When high-k dielectrics, such as Ta2O5 or TiO2 , were implemented as the dielectric of the TIT capacitor, it was difficult to suppress the leakage current because of low Schottky barrier height and poor interface due to interaction between TiN and the dielectrics. (Figure 1). On the other hand, Ru/Insulator/Ru (RIR) capacitor using high-k dielectrics has an advantage of EOT scaling down, but also has some problems yet to be solved, such as the contact-plug oxidation and Ru electrode agglomeration during the back-end process. Because tetragonal phase of HfO2 is stable at high temperature, it is important to reduce the crystallization temperature to tetragonal phase. In this study, we attempted to make tetragonal HfO2 films by atomic layer deposition using strontium doping for dielectric material of TIT capacitor. HfO2 predominantly crystallizes in the lower k monoclinic phase, instead of forming the high k tetragonal phase in pure form.[2] Therefore, it has been reported that formation of tetragonal HfO2 films by other material doping [3], and stabilizers with relatively low temperature has importance in essence. We have introduced Sr doped HfO2 thin films for high-k dielectric layers. We have investigated the crystallization behavior of Sr doped HfO2 films and electrical characteristics of TITSr doped HfO2 (Sr-HfO2 ) capacitors.

Ru/TiO2/ZrO2/TiN (RIT-TiO2/ZrO2) Capacitor Structure for the 50nm DRAM Device and beyond

Advanced Process Development Team, *Process Development Team, Semiconductor R&D Division, Samsung Electronics Co., Ltd. San#24 Nongseo-Dong, Giheung-Gu, Yongin-City, Gyeonggi-Do, Korea 449-711 E-mail: soon310.lim@samsung.com Introduction As the innovative scale-down of DRAM device continues, 50nm generation becomes close at hand. As shown in Fig. 1, to satisfy the cell capacitance of 25fF with 1.7μm storage-node height in 50nm design rule, the equivalent oxide thickness (Toxeq.) of a dielectric material should be as low as 0.8nm. TiN/HfO2/TiN (TIT) capacitor has been successfully developed for 70nm generation [1], but it seems to be difficult to meet the requirements for sub-60nm device. When Ta2O5 or TiO2 was implemented as the dielectric of the TIT capacitor to reduce Toxeq. below 1.2nm, it was difficult to suppress the leakage current because of low barrier height and poor interface between TiN and high-k dielectric (Figure 2). On the other hand, Ru/Insulator/Ru (RIR) capacitor using high-k dielectrics has some problems yet to be solved, such as the contact-plug oxidation and Ru electrode agglomeration during the back-end process. In the previous study [2], we have proposed Ru(top)/Insulator/TiN(bottom) capacitor as an alternative for the DRAM capacitor below 50nm generation. The leakage currents of Ta2O5 and TiO2 could be reduced by the application of Ru top electrode. And also a reliable storage-node was obtained with solid TiN bottom electrode. RIT-Ta2O5/HfO2 was successfully developed corresponding to Toxeq. 1.1nm with 1fA/cell leakage current after full integration. In this study, to reduce Toxeq. value lower than 0.8nm, we have introduced ZrO2 as dielectric layers. We have compared and discussed the electrical characteristics of RIT-TiO2/ZrO2 and RIT-TiO2/HfO2 capacitors. The electrical properties after back-end metal-line integration and time-dependent-dielectricbreakdown behavior were also investigated .