Jae Sub Oh

High speed Flash Memory and 1T-DRAM on dopant segregated Schottky barrier (DSSB) FinFET SONOS device for multi-functional SoC applications

A novel dopant segregated Schottky barrier (DSSB) FinFET SONOS device is demonstrated in terms of multi functioning in a high speed NAND-type flash memory and capacitorless 1T-DRAM. In addition, a novel program mechanism that uses energy band engineered hot electrons (EBEHE) energized by sharp energy band bending at the edge of source/drain (S/D) is proposed for a high speed flash memory programming operation. A short program time of 100 ns and a low program voltage of 12 V yield a Vth shift of 3.5 V and a retention time exceeding 10 years. For multi functioning, the operation of a capacitorless 1T-DRAM is also demonstrated with a partially silicided DSSB in the same device.

Sub-5nm All-Around Gate FinFET for Ultimate Scaling

Sub-5nm all-around gate FinFETs with 3nm fin width were fabricated for the first time. The n-channel FinFET of sub-5nm with 1.4nm HfO2 shows an IDsat of 497muA/mum at VG=V D=1.0V. Characteristics of sub-5nm transistor are verified by using 3-D simulations as well as analytical models. A threshold voltage increases as the fin width reduces by quantum confinement effects. The threshold voltage shift was fitted to a theoretical model with consideration of the first-order perturbation theory. And a channel orientation effect, based on a current-flow direction, is shown

Partially Depleted SONOS FinFET for Unified RAM (URAM)—Unified Function for High-Speed 1T DRAM and Nonvolatile Memory

Unified random access memory (URAM) is demonstrated for the first time. The novel partially depleted (PD) SONOS FinFET provides unified function of a high-speed capacitorless 1T DRAM and a nonvolatile memory (NVM). The combination of an oxide/nitride/oxide (O/N/O) layer and a floating-body facilitates URAM operation in PD SONOS FinFETs. An NVM function is achieved by FN tunneling into the O/N/O stack and, a 1T-DRAM function is achieved by excessive-hole accumulation in the PD body. The fabricated PD SONOS FinFET shows retention time exceeding 10 years for NVM operation and program/erase time below 6 ns for 1T-DRAM in a single-cell transistor. These two memory functions are guaranteed without disturbance between them.

Multiple-Gate CMOS Thin-Film Transistor With Polysilicon Nanowire

An ultimately scaled multiple-gate CMOS thin-film transistor with a polysilicon (poly-Si) nanowire demonstrates feasibility for vertical integration using multiple active layers for application in the terabit memory era. The short-channel effects are suppressed using a multiple gate to wrap around the nanowire in devices with a size of a few tenths of a nanometer. The switching and output characteristics show high device performance without a crystallization process for the poly-Si nanowire.

Energy band engineered unified-RAM (URAM) for multi-functioning 1T-DRAM and NVM

A novel fusion memory is proposed as a new paradigm of silicon based memory technology. An O/N/O gate dielectric and a floating body are combined with a FinFET, and the non-volatile memory (NVM) and high speed capacitorless 1T-DRAM are performed in a single transistor. A nitride trap layer is used as an electron storage node for NVM, and hetero-epitaxially grown Si/Si1-xGex energy band engineered bulk substrates allow excess hole storage for 1T-DRAM. Highly reliable 1T-DRAM and NVM are demonstrated.

A Bulk FinFET Unified-RAM (URAM) Cell for Multifunctioning NVM and Capacitorless 1T-DRAM

A bulk FinFET-based unified-RAM (URAM) cell technology is demonstrated for the fusion of a nonvolatile-memory (NVM) and capacitorless 1T-DRAM. An oxide/nitride/oxide layer and a floating-body are combined to perform a URAM operation in a single transistor. A buried n-well technology for NMOS allows hole accumulation for the 1T-DRAM operation in a p-type bulk substrate. The bulk FinFET URAM offers a cost-effective and fully compatible process with a conventional FinFET SONOS, and it also expedites heat dissipation. Highly reliable NVM and high-speed 1T-DRAM operation are confirmed, and it was also verified that there is no disturbance between the two memory functions.

A Unified-RAM (URAM) Cell for Multi-Functioning Capacitorless DRAM and NVM

A novel partially-depleted (PD) SONOS FinFET is demonstrated for unified function of a high speed capacitorless IT-DRAM and non-volatile memory (NVM). A floating body and O/N/O layer are combined in a single FinFET to provide multi-functional unified-RAM (URAM) operation. The fabricated URAM shows a VT window of 3 V with a retention time exceeding 10 years for NVM operation and a sensing margin of 9 muA with a program/erase time of 10 nsec for IT-DRAM operation in a single memory cell transistor.

Improvement of memory performance by high temperature annealing of the Al2O3 blocking layer in a charge-trap type flash memory device

The effect of postdeposition annealing (PDA) of the Al2O3 blocking layer in a charge-trap type memory device is investigated. Significant improvements are achieved by high temperature PDA at 1100 °C, achieving faster operation speed, good charge retention, and a wide program/erase window. Experimental evidence shows that the underlying mechanism is not the changes in the band gap of the crystallized Al2O3 but is due to the higher trap density in the Si3N4 trapping layer at a deeper energy level by the intermixing between Al2O3 and Si3N4. The reduced trapping efficiency of the annealed Al2O3 also helps improve the retention property.

Enhancement of Program Speed in Dopant-Segregated Schottky-Barrier (DSSB) FinFET SONOS for NAND -Type Flash Memory

A dopant-segregated (DS) Schottky-barrier (DSSB) FinFET SONOS for NAND flash memory with a proposed architecture is demonstrated for the first time. A DSSB technique with a nickel-silicided source/drain (S/D) is integrated in the FinFET with a 30-50-nm range of fin width. Compared with the conventional FinFET SONOS, the DSSB FinFET SONOS boasts very fast programming time with low voltage. For a programming state, hot electrons triggered by sharp band bending at the DS S/D region are used. As a result, a threshold voltage (V th) shift of 4.5 V is achieved in a fast programming time of 100 ns.

A Nanowire Transistor for High Performance Logic and Terabit Non-Volatile Memory Devices

Silicon nanowire-FET (SiNAWI-FET) for high performance logic device with consideration of current direction effects and terabit non-volatile memory (NVM) device using an 8 nm SiNAWI-NVM with oxide/nitride/oxide (ONO) and omega-gate structure is reported for the first time. N-and P-channel SiNAWI-FET showed the highest driving current on (110)/<110> crystal orientation without device rotation, whereas most 3-dimensional NMOS report higher driving current on 45deg device rotation rather than 0deg. Utilizing an 7 nm spherical nanowire on the 8 nm SiNAWI-NVM with ONO structure, 1.7 V VT-window was achieved from 12 V/80 musec program conditions with retention enhancement.