Hi-Deok Lee

A thermal inkjet printhead with a monolithically fabricated nozzle plate and self-aligned ink feed hole

A monolithic thermal inkjet printhead has been developed and demonstrated to operate successfully by combining monolithic growing of a nozzle plate on the silicon substrate and electrochemical etching of silicon for an ink feed hole. For the monolithic fabrication, a multiexposure and single development (MESD) technique and Ni electroplating are used to form cavities, orifices, and the nozzle plate. Electrochemical etching, as a back-end process, is applied to form an ink feed hole through the substrate, which is accurately aligned with the frontside pattern without any backside mask. The etch rate is nearly proportional to the current density up to 50 /spl mu/m/min. Experiments with a 50-/spl mu/m-diameter nozzle show ink ejection up to the operating frequency of 11 kHz with an average ink dot diameter of about 110 /spl mu/m for 0.3-A, 5-/spl mu/s current pulses.

Characterization of shallow silicided junctions for sub-quarter micron ULSI technology. Extraction of silicidation induced Schottky contact area

The current-voltage (I-V) characteristics of shallow silicided p/sup +/-n and n/sup +/-p junctions are presented. In the former the diode behavior was same as in nonsilicided junction, while drastic change in diode I-V was observed in the latter. The formation of Schottky contact was conclusively shown to be the root cause of the modified I-V behavior of n/sup +/-p junction in the forward bias region. Poole-Frenkel barrier lowering predominantly influenced the reverse leakage current, masking thereby the effect of Schottky contact. The leakage current in n/sup +/-p diodes was higher than in nonsilicided diodes by two orders of magnitude and this is consistent with the formation of Schottky contact via titanium or titanium-silicide penetrating into the p-substrate and generating trap sites. There is no increase in the leakage current and no formation of Schottky contact in case of the p/sup +/-n junction. The Schottky contact amounting to less than 0.01% of the total junction area and not amenable for SEM or TEM observation was extracted for the first time by simultaneous characterization of forward and reverse characteristics of silicided n/sup +/-p diode.

Accurate extraction of reverse leakage current components of shallow silicided p/sup +/-n junction for quarter- and sub-quarter-micron MOSFET's

A real, peripheral and corner leakage current densities are extracted from measured data of area, perimeter and corner intensive p/sup +/-n junctions fabricated with the quarter-micron CMOS technology using shallow trench isolation and titanium salicide. It is shown that the magnitude of corner leakage component is more than two orders of magnitude larger than those of areal and peripheral leakage components in silicided p/sup +/-n junctions at all temperature. The corner leakage component will be more and more important as the active area gets smaller in sub-quarter-micron devices.

Electrical and Physical Properties of HfO2 Deposited via ALD Using Hf ( OtBu ) 4 and Ozone atop Al2 O 3

HfO 2 films were deposited via Hf(OtBu) 4 precursor and ozone oxidant using atomic layer deposition (ALD) atop Al 2 O 3 . We report the impact of annealing conditions on the physical and electrical properties of a HfO 2 on Al 2 O 3 /SiN/Si substrate using medium-energy ion scattering spectroscopy, high-resolution transmission electron microscopy, thermal desorption spectra, and electrical measurements. Annealing temperatures influence the microstructure and impurity levels of Hf(OtBu) 4 HfO 2 /Al 2 O 3 /SiN films. The leakage currents of Al 2 O 3 -HfO 2 bilayer were decreased with the increase of annealing temperature and the structures of the bilayer did not break until 850°C. This change was closely related to the reduction of carbon and organic contamination during annealing. However, annealing at 950°C drastically degraded electrical properties due to the intermixing of the HfO 2 -Al 2 O 3 bilayer structure.

Characterization of Random Telegraph Signal Noise of High-Performance p-MOSFETs With a High-

The behavior of ID random telegraph signal (RTS) noise of a p-MOSFET with an advanced gate stack of HfO2/TaN is experimentally investigated and discussed. The ID-RTS noise is evaluated on a wafer level (100 sites) for statistical evaluation. The observed ratio of ID-RTS noise on a wafer is quite similar to that of a p-MOSFET with the conventional plasma-SiON dielectric, which means that the noise distribution on a wafer level is independent of the gate oxide structure and/or material. However, the relative magnitude of change of the drain current to the applied current (ΔID/ID) of the p-MOSFETs with high-k (HK) dielectrics is greater than that of p-MOSFETs with conventional plasma-SiON dielectrics by about six times due to the greater number of preexisting bulk traps in the HK dielectric. Therefore, ID-RTS noise and its associated 1/f noise can present a serious issue to the CMOSFET with an advanced HK dielectric for low-power analog and mixed-signal applications.

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Recently, high dosage doping on Si multi-gate field effect transistors and III–V planar structures using a self-limiting monolayer doping technique was reported to overcome challenges in scaling nano-sized transistors. The stoichiometry or composition of the capping layer was found to affect the diffusion efficiency of this process. In this work, we study the effect of a capping layer in sulfur monolayer doping on III–V junctions. Various capping temperatures and growth methods were compared. Based on the theoretical and experimental results, we suggest an optimized scheme consisting of a bi-layer capping structure. From Hall measurements and secondary ion mass spectrometry, a SiNx/BeO bi-layer capping, compared to single layer cap, exhibited the best results with a surface sheet resistance of 232 Ω/sq, junction depth of 11 nm, dopant profile abruptness of 3.5 nm/dec, electrically active S concentration of 4.9 × 1019/cm3 (=1.34 × 1013/cm2), and 3 times higher activation efficiency without significant tran...

Dielectric/Metal Gate

In this paper, thermally stable Ni germanide using a Ni-Pt(1%) alloy and TiN capping layer is proposed for high-performance Ge MOSFETs. The proposed Ni-Pt(1%) alloy structure exhibits low-temperature germanidation with a wide temperature window for rapid thermal processing. Moreover, sheet resistance is stable and the germanide interface shows less agglomeration despite high-temperature postgermanidation anneal up to 550 °C for 30 min. In addition, the surface of the Ni-Pt(1%) alloy structure is smoother than that of a pure Ni structure both before and after the postgermanidation anneal. Only the NiGe phase and no other phases such as PtxGey and NixPt1-xGey can be observed in X-ray diffraction results, but X-ray photoelectron spectroscopy shows that PtGe is formed during the postgermanidation anneal. The larger Pt atomic radius is believed to inhibit the diffusion of Ni into the Si substrate, thereby improving the thermal stability of the NiGe. The higher melting point of PtGe is also believed to improve thermal stability. Therefore, this proposed Ni-Pt(1%) alloy could be promising for high-mobility Ge MOSFET applications.

A study of capping layers for sulfur monolayer doping on III-V junctions

In this article, ytterbium (Yb) incorporation into NiGe is proposed to improve the thermal stability of Ni germanide for high-performance Ge metal-oxide-semiconductor field-effect transistors (Ge MOSFETs). The Yb/Ni/TiN structure shows suppression of NiGe agglomeration and better surface morphology than the Ni/TiN structure after a postgermanidation annealing of up to 550°C for 30 min. It is notable that Yb atoms distribute uniformly at the top region of NiGe. NiGe agglomeration was retarded by Yb incorporation, and the thermal stability of NiGe was therefore improved.

Improvement of Thermal Stability of Ni Germanide Using a Ni–Pt(1%) Alloy on Ge-on-Si Substrate for Nanoscale Ge MOSFETs

Presented in this paper is a quantum capacitance-voltage (C-V) modeling in depletion and inversion, incorporating the gate-depletion effect. The model enables fast and accurate extraction of the electrical thickness of gate oxide in deep submicron MOSFETs. The main quantum effect consists of the inversion capacitance of two-dimensional (2-D) electrons masking the true gate-oxide thickness, t/sub OX/. The quantum mechanical and gate depletion effects necessitate 6-10 /spl Aring/ equivalent oxide thickness correction, which is important for a t/sub OX/ of 4 nm or less. The classical C-V analysis is compared with the quantum results in the light of the data, highlighting the difference between the models. The model is shown in good agreement with experiments and also with numerically calculated results.

Ni Germanide Utilizing Ytterbium Interlayer for High-Performance Ge MOSFETs

An arsenic and phosphorus double implanted source/drain junction is proposed for 0.25- and sub-0.25-/spl mu/m NMOSFET technology. Arsenic is for the shallow high concentration region beneath the silicide, and phosphorus is for the slightly deeper junction to increase junction quality and to reduce junction capacitance. The arsenic and phosphorus double implantation is performed after sidewall formation. The double implanted source/drain junction shows a drastic reduction of reverse leakage current and little effect on the short channel characteristics compared with an arsenic only implanted device. Moreover, the circuit performance is improved by about 2.5%.