Ki-Won Yoo

VLSI architecture design of motion vector processor for H.264/AVC

H.264/AVC has considerably complex derivation process of motion data in comparison with that of previous video standards. It mainly results from advanced motion vector prediction process to cope with various macroblock partitions and spatial/temporal direct modes. This paper addresses the efficient hardware design of the motion vector processor of full-compliant H.264/AVC High Profile (HP) decoder and its FPGA implementation. It has the processing capability of HD1080 (1920 times 1088) at 60 frames per second (fps) that is asymptotic to Level 4.2 of the standard. To do this, several design considerations are investigated and the solutions for them are presented. The proposed design was realized with 41 K logic gates and 4,608 bits SRAM at the operating frequency of 266 MHz and was completely conformed by means of Allegro compliance bitstreams on an FPGA platform.

Analysis and complexity reduction of high efficiency video coding for low-delay communication

Bi-predictive motion compensation is an important coding tool in low-delay coding of HEVC. The proposed method reduces computational complexity about 30% by removing exhaustive bi-predictive motion estimation. The coding gain is about 6% in low-delay P coding.

Fast mode-decision for H.264/AVC based on inter-frame correlations

The H.264/AVC standard yields higher coding efficiency rates than other video coding standards. This is because it uses the rate-distortion optimization (RDO) technique, which selects the optimal coding mode and a reference frame for each macroblock (MB). In order to achieve this, the encoder has to encode a given block by exhaustively using all kinds of combinations (including different intra and inter-prediction modes). As a result, the computational complexity of video coding in H.264/AVC is extremely high. In this paper, two fast intra-/inter-mode-decision algorithms are proposed to reduce the complexity of the encoder. Both of these algorithms are based on the inter-frame correlation among adjacent pictures. For the fast intra-mode-decision, we used the intra-mode of the most-correlated MB at the reference frame to encode the current MB and the stationary property of the current MB was used for the fast inter-mode-decision. The simulation results show that the proposed algorithms significantly reduced the computational complexity with a negligible loss of PSNR and a slight increase in bitrate.

Texture featuring and indexing using matching pursuit in Radon space

The matching pursuit algorithm in Radon space to achieve texture feature extracting is presented. The dictionary for matching pursuit is designed according to the human visual system (HVS). Since the matching pursuit is performed in Radon space, featuring the texture is more suitable to HVS behavior. Computer simulation and experimental results are shown to demonstrate the proposed method is outperformed to retrieve the texture.

Lossless embedded compression algorithm with context-based error compensation for video application

With the increase of image resolution in video application, the memory bandwidth is a critical problem in video coding. An embedded compression algorithm is a technique that can compress the frame data when stored in memory. It is possible to reduce memory requirements. In this paper, we propose a lossless embedded compression algorithm with context-based error compensation to reduce the memory bandwidth requirement. Experimental results have shown at least 50% memory bandwidth reduction on average and the data reduction ratio of the proposed algorithm is up to 5% higher than previously proposed lossless embedded compression algorithm [2].

Embedded compression algorithm using error-aware quantization and hybrid DPCM/BTC coding

An embedded compression (EC) is a technique that can compress on-the-fly the frame data when stored in video memory; it has been used to effectively reduce the system memory requirements. In this paper, we propose a lossy EC algorithm that uses hybrid coding scheme of feedforward DPCM and modified four-level BTC, which aims at the target specification of the 4 × 2 block-wise random access at 50 % compression ratio. The algorithmic characteristics of the proposed algorithm are twofold: the first is the error-aware quantization scheme to definitely reduce the total error in a block and the last is the hybrid DPCM/BTC coding scheme to effectively handle various texture patterns that can occur in a block. The architectural advantage stems from the feedforward DPCM that breaks off the inherent dependency between the prediction and quantization present in the conventional DPCM, which helps reduce the implementation burden as well as speed up the overall processing. Comparative evaluation shows that the proposed algorithm outperforms the existing ones by 0.77–6.39 dB.

Fast intra-mode decision using inter-frame correlation for H.264/AVC

The H.264/AVC standard achieves higher coding efficiency than the previous video coding standards with the rate-distortion optimization (RDO) technique which selects the best coding mode and the reference frame for each macroblock (MB). As a result, the complexity and computational load have been significantly increased. In this paper, a novel fast intra-mode decision algorithm is proposed to reduce the complexity of the video compression, which is based on the MBpsilas stationary property and the relationship of the selected modes among adjacent pictures. Experimental results show that the proposed scheme can significantly improve the speed of an intra prediction with almost zero degradation in terms of the peak signal to noise ratio (PSNR) and generated bits.

Multi-algorithm targeted low memory bandwidth architecture for H.264/AVC integer-pel motion estimation

This paper presents a hardware oriented algorithm and its architecture of an integer-pel motion estimation for H.264/AVC. A variation of search algorithm from full search to fast search can be realized on a common framework in the proposed architecture. Proposed motion estimation architecture has a capability of real-time processing for 1080@60P with 2 reference frames and a search range of [-2048, +2047] in the horizontal and [-64, +63] in the vertical direction at the operating frequency of 266 MHz.

A probabilistic-based CU size pre-determination method for parallel processing of HEVC encoders

The advent of the state-of-the-art video coding standard, High Efficiency Video Coding (HEVC) is expected to bring great changes to relevant fields of broadcasting, storage and communications. HEVC achieves higher coding gains compared to its previous video coding standards in terms of rate-distortion (R-D) performance with various improved coding tools. This leads to heavy computational complexity and costs to HEVC encoders and these comes as strong restrictions specially to develop H/W types of encoders that are more preferred for real-time based applications and services. In particular, the quad-tree based coding unit (CU) structures with various sizes are known to contribute to achieving high coding gains of HEVC. However, RD cost calculation for mode decision with all CU sizes cannot normally be considered in the H/W HEVC encoders for real-time operation. To overcome this, a CU size pre-determination method based on a probabilistic decision model fit to implement H/W HEVC encoders is proposed in this paper. All available CU sizes are checked before inter prediction and unnecessary CU sizes are excluded from inter prediction according to the decision model. Then inter prediction with the reduced number of CU sizes can be performed in parallel with pipeline structures. The experimental results show that the proposed method effectively determines the necessary CU sizes with negligible coding loss of 1.57% for LD (Low-delay) coding structure and 1.08% for RA (Random access) coding structure, respectively in BD-BR.

Adaptive quantization scheme using dual-interleaved scalar quantizers for image/video coding

Proposed is an adaptive scalar quantization scheme. The main advantage is to improve coding performance by suppressing the sum of absolute quantization errors (SAQE) under half the maximal SAQE, assuming that the errors have uniform distribution. This fact was proven and demonstrated, integrated into H.264.