Sangkwon Na

Event statistics and criticality-aware bitrate allocation to minimize energy consumption of memory-constrained wireless surveillance system

An event criticality-aware wireless surveillance system tries to minimize the energy consumption by adjusting the image distortion (or quality) requirement according to event criticality. In this paper, we present a novel video encoding method which scales bitrate so as to minimize the energy consumption of the wireless surveillance system while satisfying the given memory constraint. Given event statistics, memory size, and distortion requirement, the presented method gives an energy-optimal bitrate based on an analytic formulation of energy-rate-distortion (E-R-D) relationship for the target system consisting of H.264 video encoder, event detector, transceiver and memory. Experimental results show that the proposed method offers up to 59.6% (29.1% on average) energy savings compared to an existing bitrate allocation method which does not consider event statistics [14].

System-level performance analysis of embedded system using behavioral C/C++ model

Design iteration time in SoC design flow is reduced through performance exploration at a higher level of abstraction. This paper proposes an accurate and fast performance analysis method in early stage of design process using a behavioral model written in C/C++ language. We made a cycle-accurate but fast and flexible compiled instruction set simulator (ISS) and IP models that represent hardware functionality and performance. System performance analyzer configured by the target communication architecture analyzes the performance utilizing event-traces obtained by running the ISS and IP models. This solution is automated and implemented in the tool, HIPA. We obtain diverse performance profiling results and achieve 95% accuracy using an abstracted C model. We also achieve about 20 times speed-up over corresponding co-simulation tools.

1.8mW, hybrid-pipelined H.264/AVC decoder for mobile devices

To meet the performance, area and power requirement constraints of H.264/AVC, we propose a hybrid pipeline architecture, and a data reuse mechanism to reduce off-chip memory access. A 4x4 sub-macroblock pipeline architecture is optimized for low power as well as performance. The proposed H.264/AVC decoder architecture can support CIF(352x288) 30 fps videos at 6MHz with 1.8 mW @ 1.65 V, implemented in 0.18 mum technology.

Low-Power Bus Architecture Composition for AMBA AXI

A system-on-a-chip communication archi- tecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we pre- sent the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication archi- tecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.

Activity-Based Motion Estimation Scheme for H.264 Scalable Video Coding

This paper proposes a motion estimation scheme to reduce the computational complexity of multilayer motion estimation for scalable video coding. Based on the result of the motion estimation of the lower resolution layer referred to as base layer, we developed a new approach for exploring the search range of the enhancement layer with high coding efficiency. This approach is based on the activity defined as the absolute difference between the motion vector predictor and the final motion vector. Based on the correlation of the activities between neighboring layers, an inter-layer activity model was developed using a curve-fitted linear equation to exploit the activity in the base layer for deciding the search center and the search range of the enhancement layer. Each activity pair in the neighboring layers is used to associate the relevant macroblock to one of two groups; boundary region and interior region. The base-layer motion vector predictor is basically selected over all the activity regions; for each activity region, the proposed motion estimation algorithm decides whether to include the median motion vector predictor or not. Minimal sufficient search range is also decided from the inter-layer activity prediction factor that is adjusted to the given sequence. The proposed scheme reduced the execution time of motion estimation by 99.26% at the cost of 1.56% bit-rate increase and 0.048 dB peak signal-to-noise ratio (PSNR) decrease on average compared with the conventional full-search algorithm. The fast full-search block matching algorithm can also be incorporated to obtain the extra CPU time reduction in the motion estimation process. By adopting the fast full-search block matching algorithm (FFSBMA) in JSVM reference software, the CPU time was reduced by up to 91.84% and the memory bandwidth was reduced by 90% at the sacrifice of 1.27% bit-rate increase and 0.041 dB PSNR decrease on average compared with the FFSBMA only.

A Multi-layer motion estimation scheme for spatial scalability in H.264/AVC scalable extension

In this paper, we propose a fast multi-layer motion estimation algorithm for spatial scalability provided in H.264/AVC scalable extension, based on the reuse of the motion vectors from multiple spatial layers. The reused motion vector is used to set a search center and refined within a small search area. However, the reused motion vector often produces significant prediction error at object boundaries. Motion vector difference defined in the H.264/AVC standard is used to decide whether the reused motion vector is appropriate. In addition, a search range is dynamically adjusted based on the distribution of the rate-distortion cost. By using the proposed multi-layer motion estimation, we reduce the execution time of motion estimation by almost 93% at the cost of 0.01 dB PSNR decrease and 0.79% bit-rate increase.

Design of energy-aware video codec-based system

Lifetimes of battery-powered monitoring and surveillance systems are limited by the given battery capacity. This could lead either to a complete loss, or to a significant loss of quality in the recorded image, of events. In this paper, we propose a energy-aware video codec-based system design which exploits event characteristics to minimize the energy consumption through energy-aware architecture exploration. Given event statistics, the proposed energy-aware system design methodology carries out the architecture exploration of a wireless surveillance node (WSN) consisting of image sensor, event detector, video encoder, transceiver and memory. Hierarchical event detection algorithms are utilized for trade-offs between energy consumption and detection accuracy. Even if sophisticated event detection algorithms require high computational complexity, they contribute to reduce the number of false detected events. Based on operational framework of power-rate-distortion relationship analysis, we build an energy-rate-distortion optimization technique which gives an energy-optimal operating point of the video encoder under the given memory constraint. Experimental results show that the proposed method prolongs the lifetime of WSN up to 3.76 times compared to an existing bitrate allocation method which does not consider event statistics and hierarchical event detection.

Lifetime maximization of video blackbox surveillance camera

In this paper, we propose a lifetime maximization method for battery- and flash-constrained blackbox surveillance node (BSN) consisting of image sensor, event detector, video encoder, flash memory and battery. Because it is not economically feasible to transfer all the recorded images to the base station due to the limited energy in BSN, the recorded images are stored in flash memory for offline event recognition. In BSN, balancing the usage of battery and flash memory is critical to prolong the lifetime, because the shortage of either battery charge or flash capacity could lead to a complete loss of events, or a significant loss of quality in the recorded image of events. The lifetime of BSN is determined by the remaining battery charge and flash memory space. In this work, we assume that the resources of BSN, i.e., battery and flash memory are refreshed every system maintenance period (SMP). The proposed method controls the bit-rate of encoded videos and sampling rate, i.e., resolution and frame rate, to prolong the BSN lifetime till the SMP. Experimental results show that the proposed method prolongs the BSN lifetime by up to 136.36% compared with an existing bit-rate allocation method which does not consider the resource usage balancing.

An early block type decision method for intra prediction in H.264/AVC

In this paper, we propose an early block type decision method to reduce the complexity of rate-distortion (R-D) cost computation in intra prediction. Our method decides the block size early among luma 4×4, 8×8 and 16×16 with simple decision scheme. R-D cost for mode decision is used for R-D cost of a subblock ( 8×16 block ) instead of that of macroblock (MB) with the proposed encoding order for the intra prediction of 4 × 4 and 8 × 8 block. The R-D cost of a subblock consists of luma components only. Chroma components have a smaller potion of the R-D cost because they use subsampling (4∶2∶0) and there is relatively small variance among chroma pixels. Our method provides the reduction of computational complexity with average 0.04dB PSNR degradation and rate increase of less than 1% in comparison with the full search method.

Energy-aware instruction-set customization for real-time embedded multiprocessor systems

This paper presents a method to customize instruction-set for configurable multiprocessors under a given silicon area budget so that total dynamic energy consumption is minimized when dynamic voltage and frequency scaling (DVFS) is employed. The proposed method is based on Mixed-Integer Linear Programming (MILP) to select the optimal processor configurations for real-time tasks from custom instruction candidates. We have evaluated the proposed method using real-life applications and commercial configurable processors. The results show that the optimally configured multiprocessors by our method has up to 23.2% reduction of dynamic energy consumption in comparison with the multiprocessors configured by a conventional approach.