Jafar Savoj

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector

A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-/spl mu/m CMOS technology in an area of 1.1/spl times/0.9 mm/sup 2/, the circuit exhibits an RMS jitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock, and a bit-error rate of 1.28/spl times/10/sup -6/, with random data input of length 2/sup 23/-1. The power dissipation is 72 mW from a 2.5-V supply.

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector

A 10-Gb/s phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming. Fabricated in 0.18-/spl mu/m CMOS technology in an area of 1.75/spl times/1.55 mm/sup 2/, the circuit exhibits a capture range of 1.43 GHz, an rms jitter of 0.8 ps, a peak-to-peak jitter of 9.9 ps, and a bit error rate of 10/sup -9/ with a pseudorandom bit sequence of 2/sup 23/-1. The power dissipation excluding the output buffers is 91 mW from a 1.8-V supply.

Design of half-rate clock and data recovery circuits for optical communication systems

This paper describes the design of two half-rate clock and data recovery circuits for optical receivers. Targeting the data rate of 10-Gb/s, the first implementation incorporates a ring oscillator and a linear phase detector whereas the second implementation uses a multiphase LC oscillator and a bang-bang phase/frequency detector. Fabricated in 0.18-/spl mu/m CMOS technology, the power consumption of each of the circuits is less than 100 mW. The rms jitter of the output clock for the two prototypes is 1 ps and 0.8 ps, respectively, while the latter achieves a capture range of more than 14%.

A 10-Gb/s CMOS clock and data recovery circuit

A 10-Gb/s phase-locked clock and data recovery circuit incorporates a 5-GHz interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-/spl mu/m CMOS technology, the circuit exhibits an rms jitter of 6.6 ps in the recovered clock with random data input of length 2/sup 23/-1. The power dissipation is 99 mW from a 2.6-V supply.

A 24Gb/s Software Programmable Multi-Channel Transmitter

A 24Gb/s transmitter with a digital linear equalizer is implemented in 90 nm CMOS technology. It supports 4-channel Analog Multi-Tone (AMT) transmission, where each channel supports 3 GSym/Sec 4 PAM data, as well as a variety of baseband (BB) modes ranging from 2 PAM to 256 PAM. The transmitter operates at maximum rate of 24 Gb/s, dissipating 51 OmW of power in 0.8 mm2

A new technique for characterization of digital-to-analog converters in high-speed systems

In this paper, a new technique for characterization of digital-to-analog converters (DAC) used in wideband applications is described. Unlike the standard narrowband approach, this technique employs least square estimation to characterize the DAC from dc to any target frequency. Characterization is performed using a random sequence with certain temporal and probabilistic characteristics suitable for intended operating conditions. The technique provides a linear estimation of the system and decomposes nonlinearity into higher-order harmonics and deterministic periodic noise. The technique can also be used to derive the impulse response of the converter, predict its operating bandwidth, and provide far more insight into its sources of distortion

A CMOS interface circuit for detection of 1.2 Gb/s RZ data

This CMOS interface circuit is used in a radar system that digitizes the reflected signal by a multi-gigahertz analog-to-digital converter (ADC) employing Josephson junctions, producing a return-to-zero (RZ) differential binary stream with 2 mV peak-to-peak amplitude at 1.2 Gb/s. The interface amplifies, detects, and demultiplexes the signal, generating a parallel output with 1 V/sub pp/ amplitude at 150 Mb/s so the subsequent digital signal processor can receive and process the data reliably.

A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter

A 12-GS/s 8-bit Digital-to-Analog Converter (DAC) enables 24 Gb/s signaling over conventional backplane channels. Designed in a 90-nm CMOS process, the circuit occupies an area of 670 mum times 350mum and achieves INL and DNL of 0.31 and 0.28 LSB. Measured SNDR and SFDR are 41 dB and 51 dB at 750 MHz and 32.5 dB and 35 dB at 1.5 GHz. The power dissipation is 190 mW from 1-V and 1.8-V power supplies.

Time-Variant Characterization and Compensation of Wideband Circuits

Many wideband circuits use interleaving to extend bandwidth leaving them with a cyclically time-variant output. This paper describes a technique for characterization of these types of circuits based on least-squares estimation of the time-varying response of circuits. Applying the methodology to a 90-nm, 12-GS/s 8-bit digitally-equalized DAC, shows significant timing varying behavior. Furthermore, using the data obtained from characterization to construct linear time-variant compensation improves the DAC signal-to-distortion ratio by at least 6 dB.