Metha Jeeradit

A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications

A 12-GS/s 8-bit digital-to-analog converter (DAC) enables 24 Gb/s signaling over conventional backplane channels. Designed in a 90-nm CMOS process, the circuit occupies an area of 670 mum times 350 mum and achieves INL and DNL of 0.31 and 0.28LSB, respectively. Measured SNDR and SFDR are 41 dB and 51 dB at 750 MHz and 32.5 dB and 35 dB at 1.5 GHz. Measured SDR and 3-dB bandwidth using 12 GS/s random data are 32 dB and 7.1 GHz, respectively. The power dissipation is 190 mW from 1-V and 1.8-V power supplies.

Fortifying analog models with equivalence checking and coverage analysis

As analog and digital circuits have become more intertwined, we need to create a validation approach that handles both circuit types gracefully. This paper proposes a model-first approach, where one creates functional models of the analog blocks that will work in a HDL simulator, and then uses these models in the same way as HDL models are used for other standard cells: they are used in the full system validation, and the underlying implementations are validated to ensure they meet this specification. While creating functional models for the analog blocks might seem difficult, almost all analog blocks can be modeled as linear systems and we use this property to help create the required functional model.

A 24Gb/s Software Programmable Multi-Channel Transmitter

A 24Gb/s transmitter with a digital linear equalizer is implemented in 90 nm CMOS technology. It supports 4-channel Analog Multi-Tone (AMT) transmission, where each channel supports 3 GSym/Sec 4 PAM data, as well as a variety of baseband (BB) modes ranging from 2 PAM to 256 PAM. The transmitter operates at maximum rate of 24 Gb/s, dissipating 51 OmW of power in 0.8 mm2

Characterizing sampling aperture of clocked comparators

Practical simulation and measurement methods based on impulse sensitivity functions to characterize the sampling aperture of clocked comparators are demonstrated on a 90 nm CMOS testchip. The results comparing a StrongARM latch and a CML latch suggest that the StrongARM latch has a narrower aperture of 23 ps but its aperture center is more sensitive to supply (65 ps/V). The CML latch has a higher sampling gain of 88.8 dB but a lower bandwidth of 6.8 GHz.

Impulse sensitivity function analysis of periodic circuits

This paper describes an efficient method to characterize the impulse sensitivity function (ISF) of a periodic circuit via periodic AC (PAC) analysis. The paper extends the application of ISF from oscillators to other periodic circuits including flip-flops, latches, clocked comparators, and regenerative amplifiers, in order to characterize their important characteristics such as set-up and hold times, regeneration gain, metastability probability, and sampling aperture/bandwidth. Recognizing that the generalized ISF is a subset of a time-varying impulse response, the ISF is efficiently computed based on periodic time-varying system analysis techniques. Compared to the previous ISF characterization method based on transient simulations, a speed-up of ~5times is achieved.

Leveraging designer's intent: A path toward simpler analog CAD tools

Leveraging the Boolean intent of digital circuits has enabled a wide set of CAD tools that helped increase the productivity of digital designers. To increase analog designers productivity requires a similar encapsulation of designers intent for analog circuits. We argue that linear system models serve this role for almost all analog circuits, while the variables of these models may be in some transformed domains, rather than being the direct voltage/current waveforms of the circuits. We show how using these models enable new ways to design, optimize, and validate mixed-signal circuits. Even systems that reach steady states only in a stochastic sense can be analyzed as linear systems. Then a remaining issue is to ensure that the non-linear circuit reaches the intended “linear” operating point during start-up, which can be addressed by global convergence analysis.

A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter

A 12-GS/s 8-bit Digital-to-Analog Converter (DAC) enables 24 Gb/s signaling over conventional backplane channels. Designed in a 90-nm CMOS process, the circuit occupies an area of 670 mum times 350mum and achieves INL and DNL of 0.31 and 0.28 LSB. Measured SNDR and SFDR are 41 dB and 51 dB at 750 MHz and 32.5 dB and 35 dB at 1.5 GHz. The power dissipation is 190 mW from 1-V and 1.8-V power supplies.

Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system

High speed serial data transceivers often employ sophisticated communication techniques to balance out the effects of material loss and reflections. Link control hardware is required to initialize and adapt the link in a variety of signaling environments, often using loops with time constants which are orders of magnitude larger than the data unit interval (UI). This presents a big problem for the link modeling and verification, especially when link is a part of a larger digital system. We describe here the modeling and simulation method that overcomes this problem. The method is based on a standard hardware description language (HDL) and is applied to a fully adaptive, multi-mode, high-speed serial link system in a 36-channel switch fabric ASIC, designed in 0.13/spl mu/m CMOS process.

Nano-magnetic non-volatile CMOS circuits for nano-scale FPGAs (abstract only)

Nanotechnology promises to open up new ways of scaling CMOS circuits by introducing new materials. For example, a hybrid circuit of CMOS gates and carbon nano-tubes (CNT), NEMS relay logic and emerging memory devices have been proposed for future nano-scale Field Programmable Gate Arrays (FPGAs). Hybrid circuits for use as FPGA configurable logic blocks (CLBs) are often proposed in the form of crossbar array architecture. However, many of emerging devices, such as NEMS relays, are not two terminal devices and are thus difficult to be used in the crossbar. On the other hand diode-based logics that are two-terminal devices that can be used in the crossbars, lack signal gain and inversion capability, which makes logic implementation with them difficult. We present nano-magnet/CMOS hybrid circuit using Magnetic Coupled Spin-Torque Devices (MCSTDs) to solve the signal gain and signal level restoration problems, allowing a crossbar array layout to be used throughout the entire crossbar array architecture FPGA. MCSTD consists of two spin torque input devices at the perimeter of a larger output device that serve as biasing dots and manipulate the magnetic reversal energy barrier of the center spintorque device. MCSTDs can implement entire Boolean logic (NAND, NOR, XOR, XNOR and NOT) simply by changing the location of the input spin-torque device and the magnetic shape anisotropy of the center device. The unique features of this logic include: 1) nonvolatility, 2) electronic gain for fan-out and signal restoration and 3) fewer devices to realize most logic functions (i.e. a single MCSTD gate can realize the entire range of Boolean logic gates, while CMOS takes up to 4 (NAND, NOR) or 16 (XOR, XNOR) transistors). The combination of non-volatility and smaller device count leads to reduced circuit area and lower power consumption. Signal gain is achieved by using asymmetric device dimensions between input and output devices. Area and energy consumption calculation of FPGA Look-Up Table (LUT) are performed to demonstrate the merits of the presented Nano-magnetic/CMOS hybrid circuit compared to CMOS. The results show a 94% savings in area at comparable energy consumptions when compared with 32nm CMOS technology node.

Intent-leveraged optimization of analog circuits via homotopy

This paper proposes a circuit optimization approach that can ease the computational burden on the simulation-based circuit optimizers by leveraging simple design equations that reflect the designers intent. The technique is inspired by continuation methods (a.k.a. homotopy) in numerical analysis where a hard problem is solved by constructing an easier problem first and gradually refining its solution to that of the hard problem. In a circuit optimization context, the designers simplified equations for the circuit serve as the easier problem. These simplified design equations are easy to write as they need not be completely accurate and have intuitive, well-understood solutions. Nonetheless, in several circuit examples, it was found that the designers equations serve as better guidance than the conventional, fixed-point equations. As a result, the proposed approach demonstrates the better convergence to the desired solution with less computational efforts.