Jaibir Sharma

Low-Loss Broadband Package Platform With Surface Passivation and TSV for Wafer-Level Packaging of RF-MEMS Devices

Packaging of radio frequency (RF) microelectromechanical system (MEMS) devices requires a good electrical performance, and thus requires the parasitic effects of packaging to be minimal. This paper presents the design, fabrication, and characterization of improved low-loss wafer-level packaging (WLP) platform with through-silicon-via (TSV) interposer for RF-MEMS packaging. The insertion loss because of parasitic effects is reduced using optimized grounding configuration and surface passivation. The coplanar waveguide (CPW) test vehicle, high-frequency antenna, RF tuner, and film bulk acoustic resonator (FBAR) filter are fabricated and characterized using the developed WLP platform with TSV. To determine the RF performance of the package, the CPW transmission lines are fabricated on high-resistivity Si substrates, and the grounding configuration is optimized. The fabrication of the RF-MEMS WLP involves the process of a TSV cap wafer and CPW transmission lines or RF MEMS on the substrate wafer. TSV cap process includes TSV etching, void-free TSV plating, and redistribution layer postprocess on thin TSV wafer. The electrical characterization of the fabricated devices is performed. The optimized model has a wide bandwidth of 26.5 GHz and a packaging loss of 0.1 dB at 10 GHz. This implies that the effect of packaging on the performance of RF device is expected to be minor. The developed WLP platform is used for the 94-GHz antenna, RF tuner, and FBAR filter packaging and the characterization of RF-MEMS devices is presented.

A monolithic 9 degree of freedom (DOF) capacitive inertial MEMS platform

A monolithic 9 degree of freedom capacitive inertial MEMS platform is presented in this paper. This platform for the first time integrates 3 axis gyroscopes, accelerometers, and Lorentz Force magnetometers together on the same chip without using any magnetic materials. This reduces the assembly cost, and fully eliminates the need of magnetic material processing and axis misalignment calibration. The fabricated sensors, vacuum packaged (vacuum ~100mTorr) at wafer level with epi-polysilicon through silicon interposer (TSI) wafer using eutectic bonding, performed within 10% of the simulation results.

Development and evaluation of a two-level functional structure for the thin film encapsulation

This paper reports a two level capping structure for encapsulating micro-electro-mechanical system (MEMS) devices. The two level capping solves the main issue of the longer release time as well as safe sealing in thin film encapsulation (TFE). In this technique, the first cap layer has many etch holes, which were uniformly distributed on it to enhance the removal of the sacrificial layer. The second cap layer forms a cap on every etch hole in the first cap layer to protect the mass loading on MEMS devices. This technique was found to be very effective in reducing the release time of the TFE. For the 1200 µm × 1200 µm sized cavity encapsulation, this technique decreases the release time of the TFE by a factor of 24 in comparison to the sidewall located channel scheme. The presented technique also helps in reducing the size of TFE as the etch holes are uniformly distributed on the TFE itself. Wide seal rings were not required to accommodate sidewall channels.

Nano Porous Gold as a Capping Layer for Thin Film Encapsulation

This paper reports Nano Porous Gold (NPG) thin film as a cap layer for encapsulating MicroElectroMechanical System (MEMS) devices. The uniformly distributed zig-zag nanopores in the NPG cap structure reduce the release time as well as protect the MEMS devices from the mass loading during the sealing process, thus solving the two main problems in thin film encapsulation (TFE) process. Using 0.5-μm thick NPG cap in combination with silicon dioxide as sacrificial layer, we could release 400 μm×400 μm×3 μm cavities in vapor-HF within 10 min, which is 16 times faster than the TFE fabricated using a conventional sidewall located release channel with nonporous films. No mass loading and damage were noticed while sealing the cap using silicon dioxide.

Development and evaluation of the porous Au structure for the thin film encapsulation

This paper presents the application of the Nano Porous Gold (NPG) for encapsulating the MicroElectroMechanical System (MEMS) devices. The NPG was realized by selective etching of the Sn from electroplated AuSn alloy on ap articular seed layer. However, it is very difficult to form through pores during selective etching process as seed layer does not contain Sn. This seed layer acts as barrier for the application of Thin Film Encapsulation (TFE) which need through etch holes in cap layer to remove the sacrificial layer underneath. So in this paper, different seed mater ials were studied to find comptability of the material with AuSn alloy as well as their suitability in easy etching to form the through etch holes after NPG formation. Cu and Ni were found the suitable seed layer for forming the AuSn alloy. During the above study, it was found that current density for electroplating of AuSn alloy is also very important parameter to fabricate the uniform AuSn alloy. It was found that 1.25 mA/cm2 is the optimum current density to achieve the AuSn alloy for TFE application. These parameters were used for demonstration of TFE.

Cavity-enhanced sacrificial layer micromachining for faster release of thin film encapsulated MEMS

This paper reports a method for fast-release and safe-sealing of thin film encapsulation (TFE) for packaging of piezoelectric MEMS devices fabricated on cavity-SOI wafers. For fast releasing of the TFE, MEMS device trenches and the cavity below them were utilized and this combination acted as etch channels. Etchant can attack the sacrificial layer from the bottom of the MEMS device as well as side-located channels. A side-located etch channel scheme was chosen to ensure safe-sealing without mass-loading. 120 µm  ×  120 µm sized encapsulation on top of the MEMS device with eight isolation trenches connected to the cavity was released in 25 min. This is twice as fast as the TFE fabricated on bulk wafer using a similar encapsulation scheme. This reduction in release time is a consequence of a prefabricated cavity underneath the device which allows the etchant to attack the sacrificial layer at multiple locations as etchant can pass from one isolation trench to another.

A Robust Bilayer Cap in Thin Film Encapsulation for MEMS Device Application

Thin-film encapsulation (TFE) is one of the promising wafer-level packaging techniques for microelectromechanical systems (MEMS) devices. One of the drawbacks of TFE is that it is difficult to encapsulate large MEMS devices due to the downward deformation of the cap layer during the release of the TFE. This paper presents a robust bilayer cap made out of aluminum nitride (AlN)/nickel (Ni) layers, which can solve the problem of downward deformation of the cap layer. This bilayer cap provides both strength and flexibility to the TFE. This bilayer cap is simulated using ANSYS and experimentally demonstrated by encapsulating cavities as large as 1200 μm × 1200 μm with 0.5 μm AlN/0.7 μm Ni, whereas even 400 μm × 400 μm-sized TFE cannot be fabricated without cracks with a solitary 1-μm-thick AlN cap layer. Standard microfabrication processes are used for the fabrication of this bilayer cap.

Integration of AlN with molybdenum electrodes and sacrificial amorphous silicon release using XeF2

This paper presents a new post-CMOS-compatible integration scheme for AlN-based MEMS devices. The proposed scheme integrates molybdenum (Mo) bottom electrodes with an amorphous silicon (a-Si) sacrificial layer, which is etched using XeF2 to release the MEMS structures. This integration approach faces two potential issues, which are solved in this work: (i) poor adhesion of AlN with a-Si, and (ii) XeF2 attacking the Mo electrode during the removal of the a-Si sacrificial layer. The adhesion problem was solved by introducing a thin oxide layer between a-Si and AlN. The sidewalls of the Mo electrodes were protected by a 0.2 µm thick SiN spacer layer from the XeF2 attack. The robustness of the integration scheme was verified by fabricating an FBAR band pass filter. RF measurements on the FBAR band pass filter show that the proposed integration works well and can be utilized for other AlN-based MEMS devices in post-CMOS applications.

Optimization of etch-hole design for the thin film packaging

This paper reports the effect of the etch hole size, their distribution on cap layer and their quantity on the release time, down deformation of encapsulation after sealing. Uniform distribution of the etch hole in the centre of cap layer helps in reducing the release time. However, it results in a mass loading. Etch holes distributed at the edge of the Thin Film Encapsulation (TFE) help in protecting of the mass loading. However, it increases the release time of the TFE. So it is required to carefully arrange the etch holes on the cap layer in such way that mass loading on the MEMS device can be avoided and release time can also be minimized. The other aspect of this study is to check the downward deformation after sealing with a function of number of etch holes and their distribution of the cap layer. It is observed that a uniform distribution of etch hole in the cap layer helps in minimizing the stress and downward deformation of the encapsulation after the sealing process. For demonstrating the TFE, amorphous Si and SiO2 were used as a sacrificial layer and the cap layer, respectively. The etching of amorphous-Si (a-Si) sacrificial layer was performed with help of XeF2.

Wafer level packaging of RF MEMS devices using TSV interposer technology

This paper presents the design, fabrication and characterization of MEMS wafer level packaging (WLP) with TSV based silicon interposer as cap wafer. High resistivity Si wafers have been used for TSV interposer fabrication mainly to minimize the intrinsic loss of RF MEMS device due to packaging. During development of this RF MEMS WLP, many key challenging processes have been developed such as, high aspect ratio TSV fabrication, double side RDL fabrication, thin wafer handling of TSV interposer and optimization of Au-Sn based TLP bonding. There are several fabrication steps involved in the actual process flow as, a) TSV fabrication and front side RDL patterning and passivation, b) Wafer thinning and backside RDL patterning and passivation c) UBM/ seal ring solder deposition and cavity formation, and d) TLP based wafer bonding of cap TSV interposer wafer with MEMS CPW wafer. Different CPW designs with three passivation schemes have been fabricated mainly to study the effect of passivation on insertion loss and ultimately quantify the packaging insertion loss. In pre-bonding testing, effect of passivation on insertion loss is thoroughly studied. After successful fabrication of the WLP, loss of RF device characteristics due to packaging has been studied. Before and after packaging, S-parameter measurements performed on coplanar waveguides (CPW). Amongst different passivation schemes, CPW structures with poly-silicon passivation have shown better performance.