Vasarla Nagendra Sekhar

Wafer level embedding technology for 3D wafer level embedded package

This paper presents the development of wafer level embedding process for a three dimensional (3D) embedded micro wafer level package (EMWLP). Wafer level embedding process was carried out by using compression molding machine and low-cost granular epoxy molding compound (EMC). Various molding process parameters such as molding time and temperature and three EMCs of different CTEs were analyzed to achieve reliable 3D EMWLP. Several molding process issues, such as warpage, die-sweep, EMC penetration, and die-shift, were faced during embedding process development. A large warpage of more than 1 mm and die-shift of more than 600 µm were found to occur in reconstructed molded wafer. Wafer level embedding process was optimized to reduce warpage and die-shift problems. A significant reduction in warpage (∼ 30 %) and die-shift (∼ 88 %) were achieved after embedding process optimization. The detail of process optimization is presented in the paper. Reconstructed molded wafers were subjected to various reliability tests, such as thermal cycle (TC), moisture sensitivity test-level 3 (MST-L3), and highly accelerated stress test (HAST). Scanning acoustic microscopy (SAM) analysis of molded wafers was carried out to analyze the void formation and delamination in molded wafers. No major void or delamination was observed in reconstructed wafer after molding as well as after reliability tests.

Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects

Fabrication of high aspect ratio through silicon vias (TSVs) in a Si interposer and fine pitch solder microbumps on a top Si die is discussed in this paper. Chip stacking result of the Si interposer and the top Si die is also presented. TSVs with 25 μm in pitch and aspect ratio higher than 10 are etched with BOSCH process. To avoid difficulties in wetting the sidewall of the TSVs, bottom-up plating method is used to fill the TSVs with Cu. In order to fill the TSVs from bottom, the TSVs are first sealed from the bottom by plated Cu with plating current of 1 A. The plated Cu is used as a seed layer and bottom-up plating is then conducted with plating current of 0.1 A. Good filling without voids or with only tiny voids has been achieved. Electroless nickel/immersion gold is plated on top of the TSVs as under bump metallurgy pads. On the top Si die, Cu pillars/Sn caps with 16 μm in diameter and 25 μm in pitch are fabricated with electroplating method. After chip stacking, interconnections are formed between them through the solder microbumps and the TSVs.

Embedded wafer level packages with laterally placed and vertically stacked thin dies

Two embedded micro wafer level packages (EMWLP) with (1) laterally placed and (2) vertically stacked thin dies are designed and developed. 3D stacking of thin dies is illustrated as progressive miniaturization driver for multi-chip EMWLP. Both the developed packages have dimensions of 10mm × 10mm × 0.4mm and solder ball pitch of 0.4mm. As part of the work several key processes like thin die stacking, 8 inch wafer encapsulation using compression molding, low temperature dielectric with processing temperature less than 200 °C have been developed. The developed EMWLP components successfully pass 1000 air to air thermal cycling (−40 to 125 °C), unbiased highly accelerated stress testing (HAST) and moisture sensitivity level (MSL3) tests. Developed EMWLP also show good board level TC (≫ 1000 cycles) and drop test reliability results. Integration of thin film passives like inductors and capacitors are also demonstrated on EMWLP platform. Developed thin film passives show a higher Q factor when compared to passives on high resistivity silicon platform. Thermo-mechanical simulation studies on developed EMWLP demonstrate that systemic control over die, RDL and package thicknesses can lead to designs with improved mechanical reliability.

Non-destructive testing of a high dense small dimension through silicon via (TSV) array structures by using 3D X-ray computed tomography method (CT scan)

In the present study, high density TSV structures have been designed and fabricated with different diameter and depths, ranging from 2 to 60 µm and 50 to 100 µm respectively. The ratios of TSV diameter to space between TSVs are 1∶2, 1∶3 and 1∶4. Inspection of TSV structures at each processing step is very crucial to proceed to next step. 3D X-ray CT scan analysis has been employed to inspect TSV wafers at different processing steps. Detailed 3D X-ray CT scan analysis has been carried out on 20, 50 and 60 um TSV array structures. Using this method, it is possible to observe defect shape, size and distribution by conducting the virtual cross-section at desired location. Based on the detailed online failure analysis, TSV process development parameter are being fine-tuned and optimized.

Low-Loss Broadband Package Platform With Surface Passivation and TSV for Wafer-Level Packaging of RF-MEMS Devices

Packaging of radio frequency (RF) microelectromechanical system (MEMS) devices requires a good electrical performance, and thus requires the parasitic effects of packaging to be minimal. This paper presents the design, fabrication, and characterization of improved low-loss wafer-level packaging (WLP) platform with through-silicon-via (TSV) interposer for RF-MEMS packaging. The insertion loss because of parasitic effects is reduced using optimized grounding configuration and surface passivation. The coplanar waveguide (CPW) test vehicle, high-frequency antenna, RF tuner, and film bulk acoustic resonator (FBAR) filter are fabricated and characterized using the developed WLP platform with TSV. To determine the RF performance of the package, the CPW transmission lines are fabricated on high-resistivity Si substrates, and the grounding configuration is optimized. The fabrication of the RF-MEMS WLP involves the process of a TSV cap wafer and CPW transmission lines or RF MEMS on the substrate wafer. TSV cap process includes TSV etching, void-free TSV plating, and redistribution layer postprocess on thin TSV wafer. The electrical characterization of the fabricated devices is performed. The optimized model has a wide bandwidth of 26.5 GHz and a packaging loss of 0.1 dB at 10 GHz. This implies that the effect of packaging on the performance of RF device is expected to be minor. The developed WLP platform is used for the 94-GHz antenna, RF tuner, and FBAR filter packaging and the characterization of RF-MEMS devices is presented.

Effect of wafer back grinding on the mechanical behavior of multilayered low-k for 3D-stack packaging applications

To study the effect of back grinding on the mechanical properties of the active side of the die, low-k stacked wafers were grinded to four different thicknesses of 500 mum, 300 mum, 150 mum, and 75 mum by using a commercial grinding process. Nanoindentation and nanoscratch tests were performed using the Nanoindenter XP (MTS Corp. USA) on both the normal (no back grinding) and back grinded samples to analyze the failure loads, modulus, hardness and adhesive/cohesive strength, of the low-k stack. It is found that the back grinding process enhances the mechanical integrity of low-k stack as the back grinded low-k stack exhibited in terms of the higher failure load and cohesive and/or adhesive strength of grinded low-k stack than the normal low-k stack. The TEM cross-section analysis showed that the interfaces in the low-k stack of normal sample are wavy, whereas the interfaces in the low-k stack of back grinded samples are even, especially at the black diamond region. Significant densification of BD films is observed in the case of back grinded sample. Based on these results, it is believed that the thermo-mechanical stresses applied and/or generated during wafer back grinding process affect the microstructure and enhance the mechanical strength of the low-k stack.

Antenna-in-Package Design Based on Wafer-Level Packaging With Through Silicon Via Technology

In this paper, a CPW-fed antenna-in-package (AiP) operating at millimeter wave (mmWave) based on a wafer-level packaging technology with through silicon via (TSV) interconnections is proposed, designed, and measured. The designed antenna consists of two-stacked high-resistivity silicon (HRSi) substrates. One is the bottom HRSi substrate with thickness of 750 μm, which carries the slot radiator and the CPW feeding. The other one is the top HRSi substrate with thickness of 200 μm carrying a patch, which is placed on the radiating element for antenna gain and efficiency improvement. The vertical interconnects in this structure are designed using the TSVs built on a HRSi wafer, which are designed to carry the radio frequency (RF) signals up to mmWave. RF path transitions are carefully designed to minimize the return loss within 10 dB in the frequency band of concern. The designed AiP is fabricated and measured, and the measured results basically match the simulation results. It is demonstrated that a wider bandwidth and less-sensitive input impedance versus the fabrication process accuracy are obtained with the designed structure in this paper. The measured results show the radiation in the broadside of the structure with gain around 2.4 dBi from 76 to 93 GHz.

Impact of packaging design on reliability of large die Cu/low-κ (BD) interconnect

This paper presents the study on the effect of low k stacked layer, chip pad design structures, and shift pad design TM of a large die size Cu/low kappa (BDtrade) chip for improving assembly and reliability performance on organic buildup substrate FCBGA (FlipChip ball grid array). Bump shear characterization has been performed on the integrity of different stacked layer and pad structure, supported by bump shear modeling analysis. Initial reliability testing was performed on assembled package to identify the best choice of design and finally implemented on the reliability test vehicle for verification. In addition, a potential chip crack problem due to excessive warpage in FCBGA with large die assembly is examined and a simple failure criterion is proposed.

6um Pitch High Density Cu-Cu Bonding for 3D IC Stacking

For ultra-fine pitch and high density Cu pillar low temperature bonding (200°C), the surface contact between substrate and Cu pillar array is the key. Therefore, the fabrication quality of copper bump array affects severely the bonding results. The qualitative factors include (1) Cu pillar array height uniformity, (2) free of copper oxide layer, (3) Cu material property (e.g. elastic modulus, grain size), (4) certain levels of roughness and (5) even the Cu pillar with or without TSV in the wafer. In this paper, test vehicle with dia3um and pitch 6um TSV 20um thin wafer are design and fabricated. The test vehicle is used to study above major bonding contributors. Solid Cu-Cu interconnects are demonstrated with both Chip to chip (C2C) and Chip to wafer (C2W) process. The developed process is promising for high density I/O (<;10um pitch) low temperature (200°C) Cu-Cu bonding for 3D stacking.

Challenges and approaches of TSV thin die stacking on organic substrate

The requirements for high density packaging such as smaller form factor, high performance and multi functionality electronics products have resulted in electronics industry moving towards 3D System in package technology (3D SIP). Some of the main advantages of 3D SIP packaging are high volume applications, smaller form factor, better connectivity between components in a 3D package, lower noise, lower power consumption and higher operating frequencies [1]. A 3D package is a cost effective solution as it helps to save placement and routing area on board using several IC process in the same module. A stacked die SiP package offers flexibility in combining die from different fab processes into a single package. Board area savings are realized by stacking the die vertically vs a side by side approach. This package technology is mainly used where X-Y size constraint is the critical requirement. Some of the key technologies needed to enable chip stacking include silicon through-vias and high-density lead-free interconnects [2]. In the paper, 2 different reflow approaches are used for the 3 die stacked flip chip assembly (i) sequential reflow and (ii) 3 die stacked simultaneous reflow. The effect of the reflow approaches of the stacked die assembly with TSV on die warpage, solder wetting, solder voids and bonding alignment is addressed in this paper. In addition, a simple D.O.E was conducted to understand the effect of bond force on thin die stacked assembly Pb-free microbumps is also reported. Results showed that optimum bond force is important to ensure no die cracks during flip chip bonding for 3 layer stacked die. In addition to the DOE conducted to understand the effect of bonding parameters on thin stacked die assembly, the selection of flux in terms of flux tackiness, flux for good solder wetting and minimum solder voids in the flip chip assembly were also addressed in this work. Low standoff for microjoint assembly often poses a challenge for underfill dispensing process. The standoff between the microbump joint of the chip on chip flip chip bonding is usually about 15µm to 20µm. The dispensing space is tight and often with limitations on the area where underfill fluids can be dispensed. Therefore it is important to evaluate flowability, bleeding of the underfill and the void formation in the underfill for stacked die assembly. The impact of these various factors on the stacked die assembly was discussed in this paper. Finally moldable underfill is then used to encapsulate the 3 layer stacked chip on the substrate.