Jaimin Mehta

A 24mm 2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS

The RF transceiver is built on the Digital RF Processor (DRP) technology. The ADPLL-based transmitter uses a polar architecture with all-digital PM-FM and AM paths. The receiver uses a discrete-time architecture in which the RF signal is directly sampled and processed using analog and DSP techniques. A 26 MHz digitally controlled crystal oscillator (DCXO) generates frequency reference (FREF) and has a means of high-frequency dithering to minimize the effects of coupling from digitally controlled PA driver (DPA) to DCXO by de-sensitizing its slicing buffer.

A 0.8mm 2 all-digital SAW-less polar transmitter in 65nm EDGE SoC

EDGE is currently the most widely used standard for data communications in mobile phones. Its proliferation has led to a need for low-cost 2.5G mobile solutions. The implementation of RF circuits in nanoscale digital CMOS with no or minimal process enhancements is one of the key obstacles limiting the complete SoC integration of cellular radio functionality with digital baseband. The key challenges for such RF integration include non-linearity of devices and circuits, device mismatches, process parameter spread, and the increasing potential for self-interference that could be induced by one function in the SoC onto another.

An Efficient Linearization Scheme for a Digital Polar EDGE Transmitter

A new linearization scheme is proposed, which compensates for nonlinear distortions experienced in the amplitude-modulation path of a digital polar EDGE transmitter integrated in a 65-nm CMOS transceiver system-on-chip (SoC) based on the Digital RF Processor (DRP) technology. The measured amplitude and phase distortions are stored in lookup tables and used for predistortion without requiring inversion computations, thus achieving significant complexity reduction. Adaptive linear interpolation along with adaptive resolution enhancement provides the desired performance across power levels. With the presented scheme, the transmitters measured performance significantly exceeds the EDGE specifications with an error vector magnitude (EVM) of typically 3% and a close-in modulated spectrum of -64 dB at a 400-kHz offset from the carrier frequency.

Accurate self-characterization of mismatches in a capacitor array of a digitally-controlled oscillator

A programmable self-characterization technique is presented, whose purpose is to determine the extent of mismatches present in a variable-capacitor (varactor) array as part of an LC tank of a digitally controlled oscillator (DCO). The varactor array represents a digital-to-analog conversion function, such that mismatches in it cause distortion in the DCOs digital frequency tracking and modulation. The presented technique, relying exclusively on internal resources in the system-on-chip (SoC) and on dedicated software, is implemented in a 65nm CMOS Digital RF Processor (DRP) based transceiver, and demonstrates sufficient accuracy to allow relatively quick measurements of mismatches of a few percent.

An EDGE transmitter with mitigation of oscillator pulling

We propose a polar transmitter architecture that is robust to modulation-induced injection pulling of its RF oscillator by means of a built-in self compensation. A mathematical model is presented for the injection pulling mechanism, which incorporates a digitally-controlled delay circuit that minimizes injection pulling by adjusting the overall phase shift in the parasitic path between the final amplitude modulation stage (aggressor) and the RF oscillator (victim). The technique is verified in a 65-nm CMOS GSM/GPRS/EDGE SoC demonstrating compliant error vector magnitude (EVM) and modulation spectral-mask performance over process and temperature.

9.1 A 45nm CMOS RF-to-Bits LTE/WCDMA FDD/TDD 2×2 MIMO base-station transceiver SoC with 200MHz RF bandwidth

Increasing mobile data demands are pushing cellular network capacity. Massive MIMO base stations with large antenna arrays and smaller cell sizes demand higher integration in radio transceivers than what is available [1].

A Low Power and Low Quantization Noise Digital Sigma-Delta Modulator for Wireless Transmitters

Digital sigma-delta (SigmaDelta) modulators are used extensively in CMOS wireless SoC designs to achieve high-resolution data conversion while controlling the quantization noise spectrum. This paper presents an implementation of a 90nm CMOS digital low-pass SigmaDelta modulator, which has lower quantization noise and lower power consumption compared to other recent structures. A conventional digital SigmaDelta structure uses a 1-bit quantizer and generates very high quantization noise at higher frequencies. In this work, we present a low-pass digital SigmaDelta architecture with a multi-bit quantizer, which achieves very low in-band as well as out-of-band quantization noise levels. It is shown that the structure can be run at half the frequency while meeting the required noise performance and essentially delivering a better power-performance trade-off. The proposed architecture, along with the original 1-bit quantizer structure, has been synthesized in a 90nm CMOS process. Area and power consumption results are presented and a comparison between a commonly used structure and the proposed one is provided.

A Low Area and Low Power Digital Band-Pass Sigma-Delta Modulator for Wireless Transmitters

The digital sigma-delta (SigmaDelta) modulators are used extensively in CMOS wireless SoC designs to achieve high-resolution data conversion while controlling the quantization noise spectrum. This paper presents an implementation of a 90nm CMOS digital band-pass SigmaDelta modulator, running at 900 MHz. The conventional band-pass SigmaDelta structures required to achieve such noise shaping are hardware intensive and do not meet the timing requirements when synthesized in 90nm technology using a static CMOS implementation. The loop-unrolling concept was recently presented as a solution for getting required rate of operation. However, this approach requires larger area and consumes higher power. In this work, we present a new architecture to achieve the necessary noise shaping at required rate of operation. The proposed structure has the different noise transfer function (NTF) compared to conventional band-pass structures and hence it gives more control over the location of zeros. It also meets timing requirements of 900 MHz across all PVT corners and shows significant saving in area and power.

Mismatch considerations in an RF-DAC design for a digital polar EDGE transmitter

We present a systematic approach for the design and analysis of a high-resolution RF-DAC. The RF-DAC is implemented in 65 nm CMOS as an integral part of a digital polar EDGE transmitter based on the Digital-RF-Processor (DRP™). It combines the functionality of a traditional baseband DAC and a mixer. This paper addresses the issue of a transistor mismatch, which has become a key design challenge at fine geometry process nodes. A method is presented to analyze the mismatch, quantify it and relate it to the system specifications. The presented techniques are used in a commercial GSM/EDGE SoC radio, in which the transmitters wideband noise (WBN) performance significantly exceeds the EDGE specifications with more than 6 dB margin at 20 MHz offset from the carrier frequency.

Self-calibration of a power pre-amplifier in a digital polar transmitter

A built-in self-calibration and self-compensation scheme for a digital power pre-amplifier (DPA) of a mobile handset transceiver is proposed. It allows accurate internal measurements of the amplitude and phase distortions experienced in the DPA using the on-chip receiver and processor. A dynamic range of over 60 dB is achieved using multiple gain settings in the receiver. The proposed scheme, in conjunction with the transceivers digital architecture, is demonstrated in a 65-nm CMOS GSM/EDGE radio, where it allows for accurate and cost-effective self-calibration to be performed in less than 0.1 s.