Oren Eliezer

All-digital PLL and transmitter for mobile phones

We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

All-digital PLL and GSM/EDGE transmitter in 90nm CMOS

A 1.2V 42mA all-digital PLL and polar transmitter for a single-chip GSM/EDGE transceiver is implemented in 90nm CMOS. It transmits GMSK with 0.5/spl deg/ rms phase error and achieves -165dBc/Hz phase noise at 20MHz offset, with 10 /spl mu/s settling time. A digitally controlled 6dBm class-E PA modulates the amplitude and meets the EDGE spectral mask with 3.5% EVM.

A digital-to-RF-amplitude converter for GSM/GPRS/EDGE in 90-nm digital CMOS

We present the first 90-nm digital CMOS RF power amplifier. This PA contains a large array of NMOS switches, and performs a direct digital-to-RF-amplitude conversion, filtering and buffering in a fully-integrated GSM/EDGE transmitter. Power control is fully digital. 40% efficiency is obtained at 10-dBm output power from 1.4 V and it occupies 0.005 mm/sup 2/.

A 24mm 2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS

The RF transceiver is built on the Digital RF Processor (DRP) technology. The ADPLL-based transmitter uses a polar architecture with all-digital PM-FM and AM paths. The receiver uses a discrete-time architecture in which the RF signal is directly sampled and processed using analog and DSP techniques. A 26 MHz digitally controlled crystal oscillator (DCXO) generates frequency reference (FREF) and has a means of high-frequency dithering to minimize the effects of coupling from digitally controlled PA driver (DPA) to DCXO by de-sensitizing its slicing buffer.

RF Built-in Self Test of a Wireless Transmitter

RF frequency synthesizers and transmitters for wireless system-on-chips have recently migrated to low-cost deep-submicrometer CMOS processes that facilitate all-digital implementations. In addition to all the benefits of lower power, lower silicon cost, reduced board area, and improved performance that the scaled CMOS integration entails, the testing costs for RF performance and wireless standard compliance could also be drastically reduced. In this brief, we propose a built-in self test (BIST) method, which is based on the premise that the internal frequency synthesizer and transmitter signals are in digital format allowing for digital signal processing to ascertain the RF performance without external test equipment. With the RF BIST capability, millions of SoCs can be calibrated and tested in a production environment using a low cost digital tester while benefiting from increased test coverage and reduced test time and cost. The presented techniques have been successfully implemented in two generations of commercial digital RF processors: 130-nm Bluetooth and 90-nm GSM single-chip radios

A 0.8mm 2 all-digital SAW-less polar transmitter in 65nm EDGE SoC

EDGE is currently the most widely used standard for data communications in mobile phones. Its proliferation has led to a need for low-cost 2.5G mobile solutions. The implementation of RF circuits in nanoscale digital CMOS with no or minimal process enhancements is one of the key obstacles limiting the complete SoC integration of cellular radio functionality with digital baseband. The key challenges for such RF integration include non-linearity of devices and circuits, device mismatches, process parameter spread, and the increasing potential for self-interference that could be induced by one function in the SoC onto another.

Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS

We propose a new multirate architecture of an all-digital PLL (ADPLL) featuring phase/frequency modulation capability. While the ADPLL approach has already proven its benefits of power dissipation and cost reduction through the discrete-time operation and full RF-SoC integration in nanoscale CMOS, the coarse discretization of the phase detector function tends to keep it from reaching the ultimate of the RF performance potential. The proposed ADPLL features an arbitrarily high data rate modulation that is independent from the reference frequency. It is also made substantially free from injection pulling and ill-shaped quantization noise of the TDC by means of dithering with dynamic adjustment of differential pair mismatches as well as frequency translation of the feedback clock. Low power techniques, such as speculative clock retiming and asynchronous counter are used. The presented ADPLL is implemented in 65 nm CMOS as part of a single-chip GSM/EDGE RF-SoC. It occupies 0.35 mm2 and consumes 32 mA of current at 1.2 V supply in the low frequency band. The measured results show a virtually spur-free operation.

Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS

This paper proposes and describes a new software and application programming interface view of an RF transceiver. It demonstrates benefits of using highly programmable digital control logic in an RF wireless system realized in a digital nanoscale CMOS process technology. It also describes a microprocessor architecture design in Digital RF Processor (DRPTM) and how it controls calibration and compensation for process, temperature and voltage variations of the analog and RF circuits to meet the required RF performance. A few calibration examples to reduce a DCO bias current and improve device reliability, as well as to optimize transmit modulation and receive performance, are given. The presented circuits and techniques have enabled successful implementation of a commercial single-chip GSM radio in 90 nm CMOS.

A Phase Domain Approach for Mitigation of Self-Interference in Wireless Transceivers

A novel approach for mitigation of self-interference in highly-integrated wireless transceivers is presented. Several examples of possible applications of this approach in a wireless cellular transceiver system-on-chip (SoC) are listed, and the application of one example is presented in detail. Mathematical analysis, simulation results, measurements, and implementation details are provided for the demonstrated technique, which was designed to minimize jitter induced onto the reference clock of a GSM transceivers PLL. Excessive jitter on this clock, caused by multiple RF aggressors centered at harmonics of it, creates amplified in-band phase-noise at the RF output of the PLL, resulting in failures in the transmitters performance. The identification of this highly complex interference mechanism, which represents a significant part of this work, is discussed in detail, as is the implemented solution. The presented phase-adjustment technique, leveraging specific features of the digitally intensive PLL and available digital-signal-processing resources, is demonstrated in a GSM system-on-chip (SoC) based on the Digital RF Processor (DRPtrade) technology in 90 nm CMOS. As it does not involve dedicated hardware, nor does it noticeably increase the current consumption, it represents a cost-free solution in the final product.