Sameh Rezeq

All-digital PLL and transmitter for mobile phones

We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

All-digital PLL and GSM/EDGE transmitter in 90nm CMOS

A 1.2V 42mA all-digital PLL and polar transmitter for a single-chip GSM/EDGE transceiver is implemented in 90nm CMOS. It transmits GMSK with 0.5/spl deg/ rms phase error and achieves -165dBc/Hz phase noise at 20MHz offset, with 10 /spl mu/s settling time. A digitally controlled 6dBm class-E PA modulates the amplitude and meets the EDGE spectral mask with 3.5% EVM.

A digital-to-RF-amplitude converter for GSM/GPRS/EDGE in 90-nm digital CMOS

We present the first 90-nm digital CMOS RF power amplifier. This PA contains a large array of NMOS switches, and performs a direct digital-to-RF-amplitude conversion, filtering and buffering in a fully-integrated GSM/EDGE transmitter. Power control is fully digital. 40% efficiency is obtained at 10-dBm output power from 1.4 V and it occupies 0.005 mm/sup 2/.

A 24mm 2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS

The RF transceiver is built on the Digital RF Processor (DRP) technology. The ADPLL-based transmitter uses a polar architecture with all-digital PM-FM and AM paths. The receiver uses a discrete-time architecture in which the RF signal is directly sampled and processed using analog and DSP techniques. A 26 MHz digitally controlled crystal oscillator (DCXO) generates frequency reference (FREF) and has a means of high-frequency dithering to minimize the effects of coupling from digitally controlled PA driver (DPA) to DCXO by de-sensitizing its slicing buffer.

A 0.8mm 2 all-digital SAW-less polar transmitter in 65nm EDGE SoC

EDGE is currently the most widely used standard for data communications in mobile phones. Its proliferation has led to a need for low-cost 2.5G mobile solutions. The implementation of RF circuits in nanoscale digital CMOS with no or minimal process enhancements is one of the key obstacles limiting the complete SoC integration of cellular radio functionality with digital baseband. The key challenges for such RF integration include non-linearity of devices and circuits, device mismatches, process parameter spread, and the increasing potential for self-interference that could be induced by one function in the SoC onto another.

An Efficient Linearization Scheme for a Digital Polar EDGE Transmitter

A new linearization scheme is proposed, which compensates for nonlinear distortions experienced in the amplitude-modulation path of a digital polar EDGE transmitter integrated in a 65-nm CMOS transceiver system-on-chip (SoC) based on the Digital RF Processor (DRP) technology. The measured amplitude and phase distortions are stored in lookup tables and used for predistortion without requiring inversion computations, thus achieving significant complexity reduction. Adaptive linear interpolation along with adaptive resolution enhancement provides the desired performance across power levels. With the presented scheme, the transmitters measured performance significantly exceeds the EDGE specifications with an error vector magnitude (EVM) of typically 3% and a close-in modulated spectrum of -64 dB at a 400-kHz offset from the carrier frequency.

Curse of digital polar transmission: Precise delay alignment in amplitude and phase modulation paths

Radio transmitters using the polar scheme utilize a CO-ORDInate Calculator (CORDIC) to transform the often interpolated baseband data in Cartesian format to its polar equivalent. This non-linear transmission typically results in an increased bandwidth for amplitude and phase modulated signals. In case of digital implementation, each of these amplitude and phase/frequency modulation paths are realized using segmented modulators, with fine resolution achieved by techniques such as sigma-delta modulation. This paper first describes the structure of a digital polar transmitter. This is followed by a study on the impact of the increased bandwidth in the polar domain on the timing alignment accuracy requirements between the amplitude and phase modulation paths. Furthermore, for each high-resolution modulation path the timing accuracy between the integer and the sigma-delta fractional path split is also analyzed.

Sigma-delta noise shaping for digital-to-frequency and digital-to-RF-amplitude conversion

In this paper, we describe a new architecture of high-speed multibit /spl Sigma//spl Delta/ noise shaping for digital-to-frequency conversion (DFC) and digital-to-RF-amplitude conversion (DRAC). The DFC and DRAC are instrumental in performing phase modulation (PM) and amplitude modulation (AM) of an RF polar transmitter. Since current biasing and continuous-time analog filtering of a conventional transmit modulator are avoided in this all-digital architecture, it is amenable to large-scale integration in an SoC realized in a digital deep-submicron CMOS process. The approach is demonstrated in the first single-chip fully-compliant GSM/EDGE transceiver realized in 90-nm CMOS.

Implementation of a high speed digital band-pass sigma-delta modulator for a wireless transmitter

Digital sigma-delta modulators are used extensively in CMOS wireless SoC designs to achieve high-resolution data conversion while controlling the quantization noise spectrum. This paper presents an implementation of a 90 nm CMOS digital band-pass sigma-delta modulator (SDM), running at 900 MHz. Conventional sigma-delta structures required to achieve such noise shaping are hardware intensive and do not meet the timing requirements when synthesized in 90 nm technology using a static CMOS implementation. In this work, we present an unrolled /spl Sigma//spl Delta/ architecture to achieve the necessary rate of operation. Unrolling is achieved by running two loops at half the frequency, while maintaining algorithmic equivalency between the original and proposed structures. The proposed architecture meets timing requirements of 900 MHz across all PVT corners at the cost of increase in area. The operating frequency for most of the hardware is halved, resulting in a 20% power consumption reduction.

Self-calibration of a power pre-amplifier in a digital polar transmitter

A built-in self-calibration and self-compensation scheme for a digital power pre-amplifier (DPA) of a mobile handset transceiver is proposed. It allows accurate internal measurements of the amplitude and phase distortions experienced in the DPA using the on-chip receiver and processor. A dynamic range of over 60 dB is achieved using multiple gain settings in the receiver. The proposed scheme, in conjunction with the transceivers digital architecture, is demonstrated in a 65-nm CMOS GSM/EDGE radio, where it allows for accurate and cost-effective self-calibration to be performed in less than 0.1 s.