Gennady Feygin

A 24mm 2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS

The RF transceiver is built on the Digital RF Processor (DRP) technology. The ADPLL-based transmitter uses a polar architecture with all-digital PM-FM and AM paths. The receiver uses a discrete-time architecture in which the RF signal is directly sampled and processed using analog and DSP techniques. A 26 MHz digitally controlled crystal oscillator (DCXO) generates frequency reference (FREF) and has a means of high-frequency dithering to minimize the effects of coupling from digitally controlled PA driver (DPA) to DCXO by de-sensitizing its slicing buffer.

LMS-based calibration of an RF digitally controlled oscillator for mobile phones

We propose a least-mean square based gain calibration technique of an RF digitally controlled oscillator (DCO) in an all-digital phase-locked loop (ADPLL). The DCO gain of about 12-kHz/least significant bit is subject to process, voltage and temperature variations, but is tracked and compensated in real time. Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wide-band frequency modulation that is independent from the ADPLL loop bandwidth. The technique is part of a single-chip fully compliant Global System for Mobile Communications (GSM)/EDGE transceiver in 90-nm digital CMOS.

A 0.8mm 2 all-digital SAW-less polar transmitter in 65nm EDGE SoC

EDGE is currently the most widely used standard for data communications in mobile phones. Its proliferation has led to a need for low-cost 2.5G mobile solutions. The implementation of RF circuits in nanoscale digital CMOS with no or minimal process enhancements is one of the key obstacles limiting the complete SoC integration of cellular radio functionality with digital baseband. The key challenges for such RF integration include non-linearity of devices and circuits, device mismatches, process parameter spread, and the increasing potential for self-interference that could be induced by one function in the SoC onto another.

A 160 MHz analog equalizer for magnetic disk read channels

This prototype filter has five taps and operates at 160 MHz clock rate, dissipating 200 mW with 5 V supply. The filter occupies 1.35 mm/sup 2/ in BiCMOS with 0.8 /spl mu/m CMOS. It uses BiCMOS sample-and-hold (S/H) circuits to derive analog discrete-time samples, and CMOS time shared sign-sign LMS (SS-LMS) for coefficient adaptation. It improves on a previous analog signal shuffling structure by: (a) fast master S/H improves the dynamic performance and reduces effect of clock jitter on timing and gain recovery, (b) additional S/H amplifiers alleviate settling time requirements and reduce power, (c) time-interleaved LMS algorithm permits low-cost and low-power coefficient adaptation. DACs for taps and for dc offset cancellation are on-chip.

A 65nm CMOS DCXO system for generating 38.4MHz and a real time clock from a single crystal in 0.09mm 2

An integrated digitally-controlled crystal oscillator (DCXO) is presented that generates both 38.4 MHz and also a 32.768 kHz real time clock (RTC) from a single 38.4 MHz crystal. The DCXO can startup independently and transition seamlessly in and out of software control. The tuning range is 280 ppm with 2 ppb/step and guaranteed monotonicity. The phase noise is -135 dBc/Hz at 1kHz offset and -146 dBc/Hz at 10 kHz offset. The current consumption is 5 mA from a 1.4 V supply in full power mode and 234 μA in low power mode, including the LDO and all clock buffers. The DCXO is implemented in standard 65 nm digital CMOS with a die area of 0.09mm2.

A low-cost quad-band single-chip GSM/GPRS radio in 90nm digital CMOS

In this paper we present a quad-band single-chip GSM/GPRS radio in 90nm digital CMOS process based on the Digital RF Processor (DRP™) technology. This chip integrates all functions from physical layer to the protocol stack and peripheral support in a single chip RF SoC. The transmitter uses a low-area small-signal digital polar architecture merging amplitude and phase information directly in an RF DAC. The receiver is based on direct RF sampling and discrete-time analog signal processing. A dedicated internal microprocessor manages the digital RF controls to provide best achievable RF performances. The transceiver exceeds all 3GPP specifications demonstrating a receive NF of 1.8 dB and a margin of 8dB on TX spectral mask at 400 KHz offset in GSM850/900 bands. The transceiver is best-in-class in area and occupies only 3.8 mm2 of silicon area.

Implementation of a high speed digital band-pass sigma-delta modulator for a wireless transmitter

Digital sigma-delta modulators are used extensively in CMOS wireless SoC designs to achieve high-resolution data conversion while controlling the quantization noise spectrum. This paper presents an implementation of a 90 nm CMOS digital band-pass sigma-delta modulator (SDM), running at 900 MHz. Conventional sigma-delta structures required to achieve such noise shaping are hardware intensive and do not meet the timing requirements when synthesized in 90 nm technology using a static CMOS implementation. In this work, we present an unrolled /spl Sigma//spl Delta/ architecture to achieve the necessary rate of operation. Unrolling is achieved by running two loops at half the frequency, while maintaining algorithmic equivalency between the original and proposed structures. The proposed architecture meets timing requirements of 900 MHz across all PVT corners at the cost of increase in area. The operating frequency for most of the hardware is halved, resulting in a 20% power consumption reduction.

Mismatch considerations in an RF-DAC design for a digital polar EDGE transmitter

We present a systematic approach for the design and analysis of a high-resolution RF-DAC. The RF-DAC is implemented in 65 nm CMOS as an integral part of a digital polar EDGE transmitter based on the Digital-RF-Processor (DRP™). It combines the functionality of a traditional baseband DAC and a mixer. This paper addresses the issue of a transistor mismatch, which has become a key design challenge at fine geometry process nodes. A method is presented to analyze the mismatch, quantify it and relate it to the system specifications. The presented techniques are used in a commercial GSM/EDGE SoC radio, in which the transmitters wideband noise (WBN) performance significantly exceeds the EDGE specifications with more than 6 dB margin at 20 MHz offset from the carrier frequency.