Jakob Lechner

A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding

This paper proposes new robust asynchronous interfaces for GALS-systems. A combination of delay-insensitive and error detecting/correcting codes is used to achieve two types of robustness: variation-tolerance and fault-tolerance. Concerning the delay-insensitive code this paper targets the well-known 4-phase dual rail code, frequently used in asynchronous circuit design. In order to enable an optimal choice of the used error detecting/correcting code, a precise fault model and a general classification of possible interconnect architectures is presented. The goal is to tolerate single-bit errors with maximum coding efficiency, i.e., with minimal overheads for interconnect resources. This is accomplished by fully utilizing the information redundancy provided by the combination of the delay-insensitive code and an appropriate error detecting/correcting code. Metastable upsets, however, cannot be handled with error correcting codes alone. Faults can occur at arbitrary times and thus compromise system timing. Even though metastability cannot be avoided, a metastability-tolerant implementation is presented, which waits for a metastable upset to resolve before processing a new data word. This guarantees correct data transmission regardless of the timing of erroneous inputs.

Muller C-Element Metastability Containment

Metastability is the source of many unexpected errors in synchronous circuits. Its mitigation is very well researched in this domain. In contrast, for asynchronous circuits it is normally assumed that the handshaking inhibits metastability. This is, however, only true within the timing closure of the circuit and in the absence of external faults. Metastability may well arise in asynchronous circuits when latching external input signals or when fault tolerance considerations require relaxing the timing closure. Therefore, this paper studies the vulnerability of asynchronous circuits to metastability at the example of a Muller-C element. Traditional mitigation techniques are applied to this kind of circuits and their fitness for Muller-C elements is analyzed.

Low Latency Recovery from Transient Faults for Pipelined Processor Architectures

Recent technology trends have made radiation-induced soft errors a growing threat to the reliability of microprocessors, a problem previously only known to the aerospace industry. Therefore, the ability to handle higher soft error rates in modern processor architectures is essential in order to allow further technology scaling. This paper presents an efficient fault-tolerance method for pipeline-based processors using temporal redundancy. Instructions are executed twice at each pipeline stage, which allows the detection of transient faults. Once a fault is detected the execution is stopped immediately and recovery is implicitly performed within the pipeline stages. Due to this fast reaction the fault is contained at its origin and no expensive rollback operation is required later on.

Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation

While stability and robustness of synchronous circuits becomes increasingly problematic due to shrinking feature sizes, delay-insensitive asynchronous circuits are supposed to provide inherent protection against various fault types. However, results on experimental evaluation and analysis of these fault tolerance properties are scarce, mainly due to the lack of suitable prototyping platforms. Using a soft-core processor as an example, this paper shows how an off-the-shelf FPGA can be used for asynchronous Four State Logic designs, on which future fault injection experiments will be conducted.

Methods for analysing and improving the fault resilience of delay-insensitive codes

Delay-insensitive (DI) codes are usually prone to transient faults occurring during an ongoing transmission. For most DI codewords even a single transient can turn an incomplete transmission into a complete codeword, which is different from the originally sent codeword. Unless further redundant information is provided, the receiver has no means to detect such a transmission fault. In this paper we therefore propose two methods to systematically increase redundancy, either by i) building resilient subcodes, or by ii) using a two-step data encoding where error detecting codes are appropriately combined with delay-insensitive codes. In contrast to existing approaches we carefully avoid the introduction of timing assumptions to mask faults. Both methods are generic and can be used for any 4-phase DI code. In this paper we apply them to m-of-n codes, Berger and Zero-Sum codes and thoroughly analyse the efficiency of the resulting coding schemes.

A Generic Architecture for Robust Asynchronous Communication Links

This paper proposes a new generic architecture for building robust communication links for globally asynchronous locally synchronous (GALS) circuits. The general idea is to use delay-insensitive codes along with error detecting codes to provide resilience against transient faults as well as robustness against delay variations. The presented link architecture is completely generic with respect to the chosen handshake protocols (2-phase/4-phase) and the used codes. Thus a specific implementation can be individually optimized regarding features such as performance, power consumption, area complexity or the number of faults that can be tolerated. In order to demonstrate the flexibility of our approach we present several solutions based on 2-phase and 4-phase dual-rail codes combined with either single parity bits or Hamming codes for error detection. In the former case the link provides resilience against single faults, in the latter double faults can be mitigated.

Enhancing pipelined processor architectures with fast autonomous recovery of transient faults

Recent technology trends have made radiation-induced soft errors a growing threat to the reliability of microprocessors, a problem previously only known to the aerospace industry. Therefore, the ability to handle higher soft error rates in modern processor architectures is essential in order to allow further technology scaling. This paper presents an efficient fault-tolerance method for pipeline-based processors using temporal redundancy. Instructions are executed twice at each pipeline stage, which allows the detection of transient faults. Once a fault is detected the execution is stopped immediately and recovery is implicitly performed within the pipeline stages. Due to this fast reaction the fault is contained at its origin and no expensive rollback operation is required later on.

Towards Comparing the Robustness of Synchronous and Asynchronous Circuits by Fault Injection

As transient error rates are growing due to smaller feature sizes, designing reliable synchronous circuits becomes increasingly challenging. Asynchronous logic design constitutes a promising alternative with respect to robustness and stability. In particular, delay-insensitive asynchronous circuits provide interesting properties, like an inherent resilience to delay-faults.

Protection of Muller-Pipelines from transient faults

While it is well understood how to efficiently protect the data path in an asynchronous transmission channel against transient faults, much less is known about protecting the handshake signals along with their associated logic - mostly a Muller Pipeline - although these are equally critical for the proper function. In this paper we analyze the possible failure scenarios in the handshake of a 4-phase bundled data protocol that can arise from transient faults and systematically elaborate mitigation techniques for the resulting effects, namely single event transients and single event upsets. By simulated fault injection we show the effectiveness of the proposed extensions for protecting the channel. We take care to make these extensions themselves immune against transient faults, and we prove their proper and deadlock-free operation under fault conditions by means of model checking. Finally we show that, while providing superior coverage, our approach is in line with comparable approaches with respect to the area overhead.

Modular Redundancy in a GALS System Using Asynchronous Recovery Links

In this paper we describe a new design approach for fault-tolerant globally asynchronous locally synchronous (GALS) systems using triple modular redundancy. The paper proposes a recovery and voting mechanism that relies on asynchronous, delay-insensitive links for state exchange. Thereby the replicated module copies remain fully timing-independent and only need to be locally synchronized. This allows for extremely flexible module partitioning and placement: Triplicated modules could be arranged on a single die, or be mapped to three separate chips to minimize the risk of two copies failing at the same time. In the first part of the paper we discuss the general concept of the recovery mechanism and the requirements for the design of the GALS modules to ensure replica determinism. The second part of the paper then presents the implementation of a lightweight recovery controller, which consists of both synchronous and asynchronous components. To access the internal state of a module we re-use the scan chains, which are typically included in every synchronous circuit for testing purposes. The robustness of our solution is verified by exhaustive fault-injection experiments.