Robert Najvirt

Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs

Several asynchronous NoC implementations have been proposed in the literature so far, providing different properties based on different assumptions and flow control strategies. Most often they are presented as monolithic solutions, making it difficult to associate the different implementation details with the achieved properties, or to identify interdependencies of choices. The key contribution of this paper will be to elaborate a generic framework for requirements on and properties of asynchronous NoCs with virtual channels that shall allow to isolate specific choices and ease the comparison between existing solutions. We will demonstrate this by aligning some of the solutions from the literature to our framework. To illustrate the usefulness of our scheme we will apply it for pinpointing a deficiency in an existing protocol and systematically elaborating a way to fix this issue.

Equivalence of clock gating and synchronization with applicability to GALS communication

Pausible clocking is a very popular approach for clock domain interfacing in GALS systems. However, accuracy and stability of the ring oscillator that is central to this principle are bad. This suggests to use gated crystal oscillators instead. In this paper we will formally show that the problem of clock gating is equivalent to the synchronization problem. We will present a fundamental block diagram for a gated clock, comprising an AND gate and a synchronizer for the control input, and will give evidence that the related circuits proposed so far in the literature are instantiations of this principle. According to our equivalence proof none of these circuits can hence be free from a residual risk of metastability; typically the MTBF is determined by the synchronizer block. This stands in contrast to the pausible clocking where the arbiter can safely prevent metastable outputs. We further argue that a handshake based data transfer (without clock stopping) yields essentially the same properties wrt. MTBF and performance, while causing more localized effects in case of a metastable upset. In conclusion the use of clock gating does not seem to provide any advantages over the alternative schemes and can hence not be recommended.

The Metastable Behavior of a Schmitt-Trigger

Schmitt-Trigger circuits are the method of choice for converting general signal shapes into clean, well-behaved digital ones. In this context these circuits are often used for metastability handling, as well. However, like any other positive feedback circuit, a Schmitt-Trigger can become metastable itself. Therefore, its own metastable behavior must be well understood, in particular the conditions that may cause its metastability. In this paper we will build on existing results from Marino to show that (a) a monotonic input signal can cause late transitions but never leads to a non-digital voltage at the Schmitt-Trigger output, and (b) a non-monotonic input can pin the Schmitt-Trigger output to a constant voltage at any desired (also non-digital) level for an arbitrary duration. In fact, the output can even be driven to any waveform within the dynamic limits of the system. We will base our analysis on a mathematical model of a Schmitt-Triggers dynamic behavior and perform SPICE simulations to support our theory and confirm its validity for modern CMOS implementations. Furthermore, we will discuss several use cases of a Schmitt-Trigger in the light of our results.

On the Appropriate Handling of Metastable Voltages in FPGAs

The significant process, voltage and temperature (PVT) variations seen with modern technologies make strictly synchronous design inefficient. Asynchronous design with its flexible timing is a promising alternative, but prototyping is difficult on the available FPGA platforms which are clock centric and do not provide the required functional primitives like mutual exclusion or Muller C-elements. The solutions proposed in the literature so far work nicely in principle but cannot safely handle metastability issues that are inevitable even at some interfaces in asynchronous designs. In this paper, we propose reliable implementations of the fundamental function blocks required to safely convert potential intermediate voltage levels that result from metastability into late transitions that can be reliably handled in the asynchronous domain. These are high- and low-threshold buffers as well as a Schmitt-trigger. We give elaborate background analysis for the proposed circuits and also present the associated routing constraints to make the Schmitt-trigger circuit work properly in spite of the uncertain routing within FPGAs. Furthermore, we propose a procedure for an “in situ reliability assessment” of the specific Schmitt-trigger element under consideration, which also applies to metastability containment with high- or low-threshold buffers only. Our proof of concept is based on experimental results for both Xilinx and Altera FPGA platforms.

How to Synchronize a Pausible Clock to a Reference

Pausible clocking is an efficient means for metastability free communication in heterochronous GALS systems. State-of-the-art implementations are based on ring oscillators, which suffer from bad frequency stability and accuracy. Building a stable pausible clock by simply switching a crystal based clock source, on the other hand, has been shown to incur metastability issues, thus rendering pausible clocking no better than a conventional synchronizer approach. In this paper we propose a solution that provides the stability and accuracy of a crystal based clock while still being free from metastable upsets. It is based on a ring oscillator that can be paused and resumed just like in the traditional approach, but is synchronized with a crystal clock during its stable phases of operation. We will present an appropriate circuit implementation and carefully analyze its operation. We will give evidence that the circuit switches on and off as fast as the traditional one, and that the clock output does not suffer from metastable voltage or spurious pulses at any time.

A Generic Architecture for Robust Asynchronous Communication Links

This paper proposes a new generic architecture for building robust communication links for globally asynchronous locally synchronous (GALS) circuits. The general idea is to use delay-insensitive codes along with error detecting codes to provide resilience against transient faults as well as robustness against delay variations. The presented link architecture is completely generic with respect to the chosen handshake protocols (2-phase/4-phase) and the used codes. Thus a specific implementation can be individually optimized regarding features such as performance, power consumption, area complexity or the number of faults that can be tolerated. In order to demonstrate the flexibility of our approach we present several solutions based on 2-phase and 4-phase dual-rail codes combined with either single parity bits or Hamming codes for error detection. In the former case the link provides resilience against single faults, in the latter double faults can be mitigated.

Measuring Metastability with Free-Running Clocks

With the increasing number of clock domain crossings in modern VLSI circuits, the area, power and performance overheads introduced by synchronization have a rising impact on the overall system parameters. To minimize these overheads while still reaching the targeted system reliability, it is very important to precisely know the parameters of the circuit elements used for synchronization regarding metastability. While it is well understood, what parameters are relevant and how they can be derived from circuit models, obtained from simulation or even measured, the state of the art measurement approaches require precisely timed clock inputs. These are typically provided with expensive test equipment, on-chip clock management blocks or calibrated delay lines. This paper proposes an approach for measuring metastability parameters using uncorrelated free-running clocks only at the expense of a more challenging post-processing. The principle is closely related to sampling oscilloscopes with the same fundamental property: the measurement resolution is theoretically unbounded but proportional to the measurement time. Apart from the description of the circuit, this paper includes an analysis of the effect of clock uncertainty (jitter) on the measurement result and an experimental evaluation.

Experimental Validation of a Faithful Binary Circuit Model

Fast digital timing simulations based on continuous-time, digital-value circuit models are an attractive and heavily used alternative to analog simulations. Models based on analytic delay formulas are particularly interesting here, as they also facilitate formal verification and delay bound synthesis of complex circuits. Recently, Függer et al. (arXiv:1406.2544 [cs.OH]) proposed a circuit model based on so-called involution channels. It is the first binary circuit model that realistically captures solvability of short-pulse filtration, a non-trivial glitch propagation problem related to building one-shot inertial delays. In this work, we address the question of whether involution channels also accurately model the delay of real circuits. Using both Spice simulations and physical measurements, we confirm that modeling an inverter chain by involution channels accurately describes reality. We also demonstrate that transitions in vanishing pulse trains are accurately predicted by the involution model. For our Spice simulations, we used both UMC-90 and UMC-65 technology, with varying supply voltages from nominal down to near sub-threshold range. The measurements were performed on a special-purpose UMC-90 ASIC that combines an inverter chain with low-intrusive high-speed on-chip analog amplifiers.

A Multi-Credit Flow Control scheme for asynchronous NoCs

Credit schemes are used to establish flow control in NoCs without blocking the communication channel. In traditional implementations one credit is transmitted per data flit, so the credit channel conveys as many messages as the data channel. Our proposed multi-credit scheme transmits credits in bundles of M, yielding one credit transmission per M flits. This saves transitions on the credit channel and promises a slower, more energy efficient implementation. We investigate requirements, options and benefits of this approach; first in theory, and then in a concrete application example, in which we propose a specifically beneficial implementation. Our study confirms that, with a negligible increase in area, our scheme can reduce dynamic energy as well as bandwidth requirements for the credit channel.

Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior?

Schmitt-Trigger stages are the method of choice for robust discretization of input voltages with excessive transition times or significant noise. However, they may suffer from metastability. Based on the experience that the cascading of flip-flop stages yields a dramatic improvement of their overall metastability hardness, in this paper we elaborate on the question whether the cascading of Schmitt-Trigger stages can obtain a similar gain. We perform a theoretic analysis that is backed up by an existing metastability model for a single Schmitt-Trigger stage and elaborate some claims about the behavior of a Schmitt-Trigger cascade. These claims suggest that the occurrence of metastability is indeed reduced from the first stage to the second which suggests an improvement. On the downside, however, it becomes clear that metastability can still not be completely ruled out, and in some cases the behavior of the cascade may be less beneficial for a given application, e.g. by introducing seemingly acausal transitions. We validate our findings by extensive HSPICE simulations in which we directly cover our most important claims.