Thomas Polzer

An Approach for Efficient Metastability Characterization of FPGAs through the Designer

The efficient design of a synchronizer for a given MTBF limit heavily depends on the availability of an accurate metastability characterization of the bistables in the target technology. We propose a measurement approach for FPGAs that comes along without any specific measurement infrastructure and can hence be performed by the designer with relatively low efforts, but is yet very accurate. Our concept comprises the use of the FPGA-internal digital clock manager (DCM), calibration measurements for the latter, averaging over several parallel measurement runs, and separated analysis of different metastability cases. To demonstrate the power of our approach we present detailed measurement results for a Xilinx Virtex-4 FPGA that even show slave metastability. Furthermore, we discuss how diverse constraints can be considered to make the measurement more accurate and time efficient.

A Metastability-Free Multi-synchronous Communication Scheme for SoCs

We propose a communication scheme for GALS systems with independent but approximately synchronized clock sources, which guarantees high-speed metastability-free communication between any two peers via bounded-size FIFO buffers. The proposed approach can be used atop of any multi-synchronous clocking system that guarantees a synchronization precision in the order of several clock cycles, like our fault-tolerant DARTS clocks. We determine detailed formulas for the required communication buffer size, and prove that this choice indeed guarantees metastability-free communication between correct peers, at maximum clock speed. We also describe a fast and efficient implementation of our scheme, and calculate the required buffer size for a sample test scenario. Experimental results confirm that the size lower bounds provided by our formulas are tight in this setting.

Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip

This paper presents the architecture and a detailed design analysis of a digital measurement chip which facilitates long-term irradiation experiments of basic asynchronous circuits. It combines radiation targets like Muller C-elements and elastic pipelines as well as standard combinational gates and flip-fops with an elaborate on-chip measurement infrastructure. Major architectural challenges result from the fact that the latter must operate reliably under the same radiation conditions the target circuits are exposed to, without wasting precious die area for a rad-hard design. A measurement architecture based on multiple non-rad-hard counters is used, which we show to be resilient against double faults, as well as many triple and even higher-multiplicity faults. The analysis is done by means of comprehensive fault injection experiments, which are based on detailed Spice models of the circuits in conjunction with a standard double-exponential current injection model for single-event transients. We also provide probabilistic calculations of the sustainable particle flow rates, based on the results of a detailed area analysis in conjunction with experimentally determined cross section data for the ASIC implementation technology used. The results confirm that the overall architecture indeed supports significant target hit rates, without exceeding the resilience bound of the measurement infrastructure.

Metastability characterization for muller C-elements

We1 present an approach for experimental metasta-bility characterization of Muller C-elements. It is based on the late transition detection scheme known from flip flop characterization. Substantial additional challenges arise from the facts that with the Muller C-element the input transition to use as a reference for the output delay may change from case to case, and the error flags of the detector need to be reliably synchronized into the other timing domain. Our solution strategy involves taking measurements concurrently and sorting out irrelevant results later on. This is done based on detailed information about type and relative position of input transitions as well as type and polarity of the output transition, for the collection of all of which we propose efficient means. An example study on an FPGA platform proves the applicability and correct operation of our approach.

A Robust Asynchronous Interfacing Scheme with Four-Phase Dual-Rail Coding

This paper proposes new robust asynchronous interfaces for GALS-systems. A combination of delay-insensitive and error detecting/correcting codes is used to achieve two types of robustness: variation-tolerance and fault-tolerance. Concerning the delay-insensitive code this paper targets the well-known 4-phase dual rail code, frequently used in asynchronous circuit design. In order to enable an optimal choice of the used error detecting/correcting code, a precise fault model and a general classification of possible interconnect architectures is presented. The goal is to tolerate single-bit errors with maximum coding efficiency, i.e., with minimal overheads for interconnect resources. This is accomplished by fully utilizing the information redundancy provided by the combination of the delay-insensitive code and an appropriate error detecting/correcting code. Metastable upsets, however, cannot be handled with error correcting codes alone. Faults can occur at arbitrary times and thus compromise system timing. Even though metastability cannot be avoided, a metastability-tolerant implementation is presented, which waits for a metastable upset to resolve before processing a new data word. This guarantees correct data transmission regardless of the timing of erroneous inputs.

Muller C-Element Metastability Containment

Metastability is the source of many unexpected errors in synchronous circuits. Its mitigation is very well researched in this domain. In contrast, for asynchronous circuits it is normally assumed that the handshaking inhibits metastability. This is, however, only true within the timing closure of the circuit and in the absence of external faults. Metastability may well arise in asynchronous circuits when latching external input signals or when fault tolerance considerations require relaxing the timing closure. Therefore, this paper studies the vulnerability of asynchronous circuits to metastability at the example of a Muller-C element. Traditional mitigation techniques are applied to this kind of circuits and their fitness for Muller-C elements is analyzed.

Measuring the Distribution of Metastable Upsets over Time

As modern ASICs comprise an increasing number of independently clocked subsystems that need to interact, the accurate reliability assessment of synchronizers becomes crucial. Traditionally the reliability of a synchronizer is characterized by the mean time between upsets (MTBU), and the relevant flip-flop parameters are specified in a way to support MTBU calculation. In this paper we claim that actually a deeper insight into the distribution of upsets over time is needed in order to make a reasonable prediction in the range of the high reliability values that are generally targeted. We present a measurement concept that appropriately extends state-of-the-art approaches so as to allow for an experimental assessment of the upset distribution over time. In this way the distribution function can be studied, and in particular the probability of upsets with low temporal distance -- which is the relevant one for high reliability -- can be identified. We implement our concept on three different FPGA platforms and present the selected results. The distribution function we obtain indicates that the assumption of a uniform or standard normal distribution, which one might be tempted to imply for lack of better information, is definitely not generally useful.

SET propagation in micropipelines

Radiation-induced Single Event Transients (SETs) have the potential to create metastability in asynchronous circuits, as they are much shorter than the typical handshake cycle and do not respect the timing closure. Micropipelines have been shown to be effective in filtering those pulses. In this paper1 we investigate the propagation of pulses of critical width through a micropipeline in SPICE simulations. We study how the pipeline implementation, especially the output buffer design (matched threshold, high threshold, Schmitt-trigger) influences the propagation behavior. For the solutions with single sided thresholds we observe a considerable propagation potential of critical pulses that strongly depends, however, on the degree of threshold matching. The Schmitt trigger output, in contrast, reliably filters all pulses which are shorter than a certain threshold while propagating all others securely. At the same time our respective analysis reveals that the cost of the Schmitt trigger stage in terms of performance overheads is also significant, so the choice needs to be carefully balanced with the application requirements.

On the Appropriate Handling of Metastable Voltages in FPGAs

The significant process, voltage and temperature (PVT) variations seen with modern technologies make strictly synchronous design inefficient. Asynchronous design with its flexible timing is a promising alternative, but prototyping is difficult on the available FPGA platforms which are clock centric and do not provide the required functional primitives like mutual exclusion or Muller C-elements. The solutions proposed in the literature so far work nicely in principle but cannot safely handle metastability issues that are inevitable even at some interfaces in asynchronous designs. In this paper, we propose reliable implementations of the fundamental function blocks required to safely convert potential intermediate voltage levels that result from metastability into late transitions that can be reliably handled in the asynchronous domain. These are high- and low-threshold buffers as well as a Schmitt-trigger. We give elaborate background analysis for the proposed circuits and also present the associated routing constraints to make the Schmitt-trigger circuit work properly in spite of the uncertain routing within FPGAs. Furthermore, we propose a procedure for an “in situ reliability assessment” of the specific Schmitt-trigger element under consideration, which also applies to metastability containment with high- or low-threshold buffers only. Our proof of concept is based on experimental results for both Xilinx and Altera FPGA platforms.

Enhanced Metastability Characterization Based on AC Analysis

The common way of characterizing the metastability properties of a circuit is by its metastability resolution constant τ and the aperture window. This approach is based on a model that represents the storage cell as a pair of crosscoupled inverters, each of which is, in turn, modeled by a constant-gain amplifier with a first-order low-pass filter at the output. The former reflects the inverters signal regeneration capability, while the latter approximates its dynamic behavior. In this simple model there is no natural way of expressing, e.g., the load dependence of tau, therefore each change of the elements load capacitance requires a full recalibration. In this paper we propose decomposing the inverter into its constituent transistors and using their small-signal equivalent circuits for modeling. Metastability characterization is now based on a Spice AC analysis which yields a higher-order dynamic model of the circuit. Once the relevant parameters are known for a given element, the load dependence of tau can be expressed analytically, thus elegantly avoiding recalibration. We compare our approach with the extended nose short simulation (ENSS) method from literature and show that the results deviate by no more than 1-2%.