Lidia Łukasiak

Modeling of SiGe-base heterojunction bipolar transistor with gaussian doping distribution

Abstract The results of numerical modeling of the base transit time and collector current of SiGe-base heterojunction bipolar transistors with a Gaussian base doping profile and two Ge profiles (linearly graded and box) are presented for the first time. The importance of including the dependence of minority carrier mobility on the drift field and the dependence of the effective density of states on the Ge concentration along the base is demonstrated through the analysis of base transit time and collector current. A function describing the decrease of the density of states product in strained SiGe layers with increasing Ge concentration is proposed.

Studies of the quality of GdSiO―Si interface

Abstract In this paper nMOS transistors with GdSiO gate dielectric are studied using electrical methods ( C – V , I – V and charge pumping) in order to assess the quality of the dielectric-semiconductor interface. Mobility is estimated using the split C – V technique and the influence of voltage stress on interface trap generation and charge build-up in the oxide is investigated. Generation of additional interface traps is observed during negative voltage stress only, which may be attributed to hole tunneling from the semiconductor to electron traps. Multi-frequency charge pumping measurements reveal the presence of border traps.

The influence of bandgap narrowing on the I–V characteristics of a MOSFET

Abstract Modifications of Pierret-Shields model which take into account either apparent or physical bandgap narrowing are presented. The influence of bandgap narrowing on the I–V characteristics of a MOSFET is theoretically examined through comparison of the modified models with the original Pierret-Shields model for various device parameters. It is proved that bandgap narrowing affects significantly performance of a MOSFET in the subthreshold and the near-threshold regions.

Modeling high-frequency capacitance in SOI MOS capacitors

This paper presents a model of high frequency capacitance of a SOI MOSCAP. The capacitance in strong inversion is described with minority carrier redistribution in the inversion layer taken into account. The efficiency of the computational process is significantly improved. Moreover, it is suitable for the simulation of thin-film SOI structures. It may also be applied to the characterization of non-standard SOI MOSCAPS e.g. with nanocrystalline body.

Simulation of electrical characteristics of GaN vertical Schottky diodes

Reverse current of GaN vertical Schottky diodes is simulated using Silvaco ATLAS to optimize the geometry for the best performance. Several physical quantities and phenomena, such as carrier mobility and tunneling mechanism are studied to select the most realistic models. Breakdown voltage is qualitatively estimated based on the maximum electric field in the structure.

Influence of series resistance determination on the extracted mobility in MOS transistors with Ge channel

The influence of the method of series resistance determination on the extracted channel mobility is investigated in MOS transistors with relaxed and strained Ge channel. The dependence of the extracted mobility on the channel length and the frequency of the signal used to measure capacitance-voltage characteristics are examined.

Electrical characterization of GaN-channel MOSFETs

The channel mobility and reliability of NMOSFETs with GaN channel are investigated by means of split CV and constant-voltage-stress techniques. The influence of stress polarity and duration on current in the off-state, threshold voltage and subthreshold slope is studied.

Nanostructures applied to bit-cell devices

In this work split-gate charge trap FLASH memory with a storage layer containing 3D nano-crystals is proposed and compared with existing sub-90 nm solutions. We estimate electrical properties, cell operations and reliability issues. Analytical predictions show that for nano-crystals with the diameter < 3 nm metals could be the preferred material. The presented 3D layers were fabricated in a CMOS compatible process. We also show what kinds of nano-crystal geometries and distributions could be achieved. The study shows that the proposed memory cells have very good program/erase/read characteristics approaching those of SONOS cells but better retention time than standard discrete charge storage cells. Also dense nano-crystal structure should allow 2-bits of information to be stored.

Modeling the current of a double-gate MOSFET with very thin active region taking into account mobility dependence on the transverse electric field

Drain current and transconductance of a symmetrical, undoped double-gate MOSFET is modeled for the first time with mobility depending on both the applied voltage and position in the channel leading to analytical formulae. The obtained models are compared with simplified formulae assuming position-independent effective mobility. Good agreement is obtained in the case of one of the selected mobility models.

New threshold voltage definition for undoped symmetrical DG MOSFET

A new threshold definition is proposed for symmetrical undoped double gate MOS (DGMOS). Threshold voltage is calculated using the potential model described in [1] with only two fitting parameters, the values of which do not depend on device geometry. Comparison with the results of numerical simulations and other models of VT is presented and good accuracy of the new model is demonstrated.