Jamal Riani

3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS

High-speed signaling using NRZ has approached speeds above 50Gb/s where it is extremely difficult to maintain power efficiency and performance over a wide variety of channels and applications. PAM-4 is emerging as one way to increase throughput in such band-limited channels. Higher modulation formats help to address cost in optical systems by packing more bits/wavelength [1]. Strong momentum in standards to adopt PAM-4 reflects these significant trends in the industry. At the same time, migrating transceiver designs to current technology nodes have narrowed the power gap between traditional Analog and ADC-DSP-DAC-based systems for high-speed applications. These factors make ADC-based receivers a highly desirable choice, as is also the trend in wireless communications.

A background calibrated 28GS/s 8b interleaved SAR ADC in 28nm CMOS

A 28-GS/s time-interleaved ADC suitable for PAM4 optical and backplane applications is presented. The architecture uses a two-rank 2×(4:4) sampling network to interleave 32 8b SAR ADCs employing redundancy to relax DAC settling requirements. A DSP core estimates and corrects the gain, offset and timing error between channels. An ENOB of 5.8b and 5.4b is achieved with 1-GHz and 13.3GHz input signals. The ADC consumes 165-mW from a single 950-mV power supply and is fabricated in a 28nm CMOS process occupying 0.24mm2.