James Brinkhoff

Effect of baseband impedance on FET intermodulation

The intermodulation performance of an FET in the common-source configuration is dependent on the impedance presented to its gate and drain terminals, not only at fundamental, but also at harmonic and baseband frequencies. At baseband frequencies, these terminating impedances are usually determined by the bias networks, which may have varying impedance over the frequencies involved. This can give rise to asymmetry in two-tone intermodulation levels, and changing intermodulation levels with tone spacing, as previous studies have shown. In this paper, an FET is analyzed to gain an understanding, useful to the circuit designer, of the contributing mechanisms, and to enable the prediction of bias points and the design of networks that can minimize or maximize these effects. Compact formulas are given to facilitate this. An amplifier was tested, showing good agreement between the theoretical and measured results.

A 60-GHz OOK Receiver With an On-Chip Antenna in 90 nm CMOS

A low power 60-GHz on-off-keying (OOK) receiver has been implemented in a commercial 90 nm RF CMOS process. By employing a novel on-chip antenna together with architecture optimization, the receiver achieves a sensitivity of -47 dBm at a bit-error rate (BER) of less than 10-3. Using a commercial transmitter with transmit power of 1.5 dBm, a transmission distance of 5 cm can be achieved at 1.2 Gbps data rate. In this design, the on-chip antenna minimizes the packaging loss, while energy detection at RF allows architecture simplification. Both techniques contribute to the receivers low power consumption of 51 mW, excluding test buffers. This leads to a bit energy efficiency of 28 pj/bit at 1.8 Gbps. The total die area is 3.8 mm2 with the on-chip antenna occupying almost half of it.

Scalable Transmission Line and Inductor Models for CMOS Millimeter-Wave Design

A new equivalent-circuit model for transmission lines and inductors on silicon is proposed. The SPICE-compatible model is suitable for time-domain simulators. It is able to fit the frequency-dependent behavior of the RLGC parameters well into the millimeter-wave range. The model is extracted from electromagnetic simulations with a simple analytic procedure with no need for tuning or optimization. A method for making the model scalable with both line length and width (or inductor diameter) is proposed. Based on this new model, a scalable measurement deembedding methodology is proposed, that can greatly reduce wafer area needed for test and deembedding structures. The fully scalable model results are compared with measurements of devices fabricated in a 90 nm CMOS process.

On the Deembedding Issue of CMOS Multigigahertz Measurements

The purpose of this paper is to address the issues of deembedding multigigahertz CMOS measurements by extensively comparing six popular methods and by proposing a new method based on two-port measurements. The comparison aims to evaluate the maximum applicable frequency of equivalent-circuit methods (open-short, three step, ...) and the effect of the source dangling leg of MOSFETs on the cascade methods (two line and thru). Fifty dummy structures and 12 MOSFETs were fabricated using standard 0.18-mum CMOS technology. It was found that, at low frequencies (<6 GHz), all method results were comparable. The open-short method performed well over the entire frequency range (0.1-40 GHz) studied. The newly developed method, called the thru-short method, uses only two dummy structures, a thru and a short, to completely deembed the parasitics from probe pads, interconnects, and the semiconducting substrate. The measurements validated the thru-short algorithm and showed its usefulness for multigigahertz on-wafer CMOS measurements.

Millimeter-Wave Passives in 45-nm Digital CMOS

With dramatically increased ft and fmax, CMOS technologies have been widely applied in the design of millimeterwave circuits. To reduce the fabrication cost, digital CMOS processes may be used. Due to the lack of thick top metal and the reduced distance between the top metal and silicon substrates in a digital CMOS, the design of high-performance passives becomes very challenging, particularly in the millimeter-wave frequency regime. In this letter, passives with novel structures were fabricated in a 45-nm digital CMOS process. These passives, including transmission lines, spiral inductors, and metal-oxide-metal (MOM) capacitors, were designed and characterized up to 110 GHz. Their performance was compared with those fabricated using 180- and 90-nm RF CMOS processes. These passives achieved good performance in the millimeter-wave regime. A MOM capacitor has a self-resonant frequency higher than 110 GHz. An inductor achieves a quality factor of 24 at 70 GHz. These results show the feasibility of implementing the millimeterwave passives and systems in a 45-nm digital CMOS process.

Baseband impedance and linearization of FET circuits

Baseband impedance has been identified as having a positive or negative effect on the intermodulation distortion of microwave circuits. The effect can be assessed or utilized with the aid of previously proposed figures-of-merit. Under certain situations, intermodulation cancellation can be achieved simply by adding resistance to the bias network. The impact of baseband impedance on the performance of derivative superposition amplifiers is analyzed. A bias region was studied that exhibits a good second- and third-order intermodulation null with minimal intermodulation dependence on baseband impedance. This allows the effective use of the derivative superposition technique in baseband amplifiers, as well as giving wide-band linearization performance in RF amplifiers.

On-Chip Coupled Transmission Line Modeling for Millimeter-Wave Applications Using Four-Port Measurements

Transmission lines are fundamental elements in millimeter-wave circuits. In this paper, on-chip coupled transmission lines, fabricated in a commercial 0.18 ¿m complementary metal-oxide semiconductor process, have been modeled, based on measured 50 GHz four-port scattering-parameters. The two-port open-short deembedding technique and thru deembedding method were successfully extended and applied to the four-port structures presented here. The accuracy of the deembedding techniques was verified by full-wave electromagnetic simulation. Based on the deembedded S-parameters, a SPICE-compatible equivalent circuit model of on-chip coupled transmission lines was extracted. Simulation and measurement results agree well over the entire frequency band from 100 MHz up to 50 GHz.

A New Six-Port Transformer Modeling Methodology Applied to 10-dBm 60-GHz CMOS ASK Modulator Designs

This paper presents a new broadband equivalent-circuit model for millimeter-wave transformers on silicon. The model includes a center tap on the primary and secondary, and considers coupling between all segments of the windings. A corresponding methodology to analytically extract the model from electromagnetic (EM) simulations is developed. The broadband model is verified by EM simulations and measurements. Two amplitude modulatable power oscillators with high power efficiency are demonstrated using low-loss transformers. One achieves an output power of 10.4 dBm near 57 GHz with a total efficiency of 23.6%. Applying amplitude-shift keying modulation, their maximum data rate exceeds 2 Gb/s. Simulations of these circuits showed the transformer model performs well in time-domain simulations.

Integration of SiP-Based 60-GHz 4

An integrated system-in-package-based 60-GHz 4 × 4 antenna array with CMOS on-off keying (OOK) transmitter and low-noise amplifier (LNA) is investigated. The 4 × 4 circular polarized array exhibits a wide impedance bandwidth (VSWR <; 2) and 3-dB axial ratio bandwidth of over 8 GHz using a strip line sequential rotation feeding scheme. It has a beam-shaped pattern with a 3-dB beamwidth of 20° and a peak gain of 16.8 dBi. The modulators in 90-nm CMOS includes 60-GHz oscillators and switchable amplifiers to achieve the OOK modulation. The key features of the circuits are small power consumption and size. By applying a bond wire compensation scheme, the LNA and 60-GHz CMOS modulator are successfully integrated into the low-temperature co-fired ceramic package with 2-mil 500-μm-long bond wires. The measurement results for the antenna array with LNA shows a peak gain of ~ 35 dBi. The 60-GHz CMOS modulator is tested at a data rate of 2 Gb/s and the bit-error performance of the system is also demonstrated. The energy usage of 60-GHz modulator at 2 Gb/s is only 13.2 pj/bit for the modulator.

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Charge trapping effects in high electron mobility transistors (HEMTs) are linked to anomalous intermodulation behavior, known as memory effects. This behavior can be observed clearly as changes in intermodulation levels with tone-spacing, and two-tone asymmetry. A Volterra-series analysis of an HEMT with trapping predicts the distortion accurately, and allows an understanding of the mechanisms involved.