Jinglin Shi

Millimeter-Wave Bandpass Filters by Standard 0.18-

Millimeter-wave (mm-wave) bandpass filters are presented using the standard 0.18-mum CMOS process. Without any postprocessing steps, thin film microstrip (TFMS) structure is properly constructed on the low-resistivity silicon substrate, aiming at reducing the substrate loss and crosstalk to a large extent. Using the broadside-coupled scheme, a tight coupling is achieved so as to make up a class of low-loss and broadband TFMS bandpass filters in the mm-wave range. To achieve a small size, one-stage and two-stage filters with sinuous-shaped resonators are designed and fabricated. A good agreement between the predicted and measured results has been observed up to 110 GHz

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The purpose of this paper is to address the issues of deembedding multigigahertz CMOS measurements by extensively comparing six popular methods and by proposing a new method based on two-port measurements. The comparison aims to evaluate the maximum applicable frequency of equivalent-circuit methods (open-short, three step, ...) and the effect of the source dangling leg of MOSFETs on the cascade methods (two line and thru). Fifty dummy structures and 12 MOSFETs were fabricated using standard 0.18-mum CMOS technology. It was found that, at low frequencies (<6 GHz), all method results were comparable. The open-short method performed well over the entire frequency range (0.1-40 GHz) studied. The newly developed method, called the thru-short method, uses only two dummy structures, a thru and a short, to completely deembed the parasitics from probe pads, interconnects, and the semiconducting substrate. The measurements validated the thru-short algorithm and showed its usefulness for multigigahertz on-wafer CMOS measurements.

CMOS Technology

This paper investigates the design and implementation of millimeter-wave narrow-bandpass filters in a standard 0.18- m CMOS technology. Filters with a measured 10% 3-dB bandwidth at 60 and 77 GHz are realized in a thin-film microstrip structure by using the lowest metallization layer as a ground plane. The impact of dissipation losses of the filters is also examined. It is found that the metallization losses in the coupled-line filter as well as the ground plane are the main reasons for the insertion loss.

On the Deembedding Issue of CMOS Multigigahertz Measurements

The through silicon via (TSV) technology provides a promising option to realize a compact millimeter-wave (mmW) and terahertz (THz) system with high performance. As the fundamental elements in this system, transmission lines (T-lines) and interconnects are very important and therefore studied in this paper. A TSV-based substrate integrated waveguide (SIW) is also characterized. The results show that, the T-lines and interconnects are viable at frequencies lower than ~150 GHz whereas SIW can operate relatively well up to 300 GHz. In addition, two mmW components, i.e., a hairpin filter and a patch antenna, are designed by the TSV technology. Results of all the above passive components indicate that the low-resistivity silicon is the main cause of the total loss. Afterwards, two novel TSV-based topologies are proposed to efficiently integrate an antenna with active circuits for the mmW and THz applications.

Design of 60- and 77-GHz Narrow-Bandpass Filters in CMOS Technology

In modern CMOS technologies, metal dummy fills are required to maintain metal density uniformity and to planarize the layers. As frequency increases, the effect of the metal dummy fills on the CMOS integrated circuits or components should be taken into account. This work presents experimental results of the effect of metal dummy fills on the microwave behavior of spiral inductors fabricated in a standard 0.18-mum CMOS technology. The influences on the equivalent model parameters and the Q-factor are characterized based on measured S-parameters of inductors with and without metal dummy fills.

TSV Technology for Millimeter-Wave and Terahertz Design and Applications

A fully scalable and SPICE compatible wideband model of on-chip interconnects valid up to 110 GHz is presented in this paper. The series branches of the proposed multisegment model consist of an RL ladder network to capture the skin and proximity effects, as well as the substrate skin effect. Their values are obtained from a technique based on a modified effective loop inductance approach and complex image method. A CG network is used in the shunt branches of the model, which accounts for capacitive coupling through the oxide and substrate loss due to the electrical field, as well as the impact of dummy metal fills. The values of these elements are determined by analytical and semiempirical formulas. The model is validated by a full-wave electromagnetic field solver, as well as measurements. The simulated S-parameters of the model agree well with the measured S-parameters of on-chip interconnects with different widths and lengths over a wide frequency range from dc up to 110 GHz.

Experimental Characterization of the Effect of Metal Dummy Fills on Spiral Inductors

Extensive studies on the performance of on-chip CMOS transformers with and without patterned ground shields (PGSs) at different temperatures are carried out in this paper. These transformers are fabricated using 0.18-mum RF CMOS processes and are designed to have either interleaved or center-tapped interleaved geometries, respectively, but with the same inner dimensions, metal track widths, track spacings, and silicon substrate. Based on the two-port S-parameters measured at different temperatures, all performance parameters of these transformers, such as frequency- and temperature-dependent maximum available gain (Gmax), minimum noise figure (NFmin), quality factor (Q1) of the primary or secondary coil, and power loss (Ploss) are characterized and compared. It is found that: 1) the values of the Gmax and Q1 factor usually decrease with the temperature; however, there may be reverse temperature effects on both G max and Q1 factor beyond certain frequency; 2) with the same geometric parameters, interleaved transformers exhibit better low-frequency performance than center-tapped interleaved transformers, whereas the center-tapped configurations possess lower values of NFmin at higher frequencies; and 3) with temperature rising, the degradation in performance of the interleaved transformers can be effectively compensated by the implementation of a PGS, while for center-tapped geometry, the shielding effectiveness of PGS on the performance improvement is ineffective

A Wideband Scalable and SPICE-Compatible Model for On-Chip Interconnects Up to 110 GHz

Vertical topologies of on-chip silicon miniature multispiral stacked inductors are addressed, which have been fabricated by a 0.18-mum CMOS process. A generalized topological circuit model is first developed with mutual capacitive and inductive couplings treated appropriately. A set of analytical equations is given for calculating all mutual frequency-independent (dc) inductances among different spirals. The partial-element equivalent-circuit method is implemented for capturing frequency- and temperature-dependent resistances and inductances (ac) of arbitrary spiral-stacked geometries by which mutual inductive coupling between different spirals are investigated. According to the fabricated four- to six-spiral stacked inductors and the measured two-port S parameters, modeling and experimental studies are carried out so as to verify applicability and scalability of the proposed topological model. Excellent agreement between them are achieved in the characterization of inductances and factors of all samples beyond their self-resonant frequencies.

Frequency-Thermal Characterization of On-Chip Transformers With Patterned Ground Shields

With dramatically increased ft and fmax, CMOS technologies have been widely applied in the design of millimeterwave circuits. To reduce the fabrication cost, digital CMOS processes may be used. Due to the lack of thick top metal and the reduced distance between the top metal and silicon substrates in a digital CMOS, the design of high-performance passives becomes very challenging, particularly in the millimeter-wave frequency regime. In this letter, passives with novel structures were fabricated in a 45-nm digital CMOS process. These passives, including transmission lines, spiral inductors, and metal-oxide-metal (MOM) capacitors, were designed and characterized up to 110 GHz. Their performance was compared with those fabricated using 180- and 90-nm RF CMOS processes. These passives achieved good performance in the millimeter-wave regime. A MOM capacitor has a self-resonant frequency higher than 110 GHz. An inductor achieves a quality factor of 24 at 70 GHz. These results show the feasibility of implementing the millimeterwave passives and systems in a 45-nm digital CMOS process.

Vertical Topologies of Miniature Multispiral Stacked Inductors

Using the complex image method (CIM), we have analyzed the frequency and temperature dependencies of substrate eddy currents for single-ended and differential spiral inductors on a lossy silicon substrate. From our analysis, we have derived a set of accurate closed-form expressions for calculating inductances and substrate losses due to substrate eddy currents. Here, we propose a frequency-dependent eleven-element equivalent circuit model based on these formulas. We established the validity of the model by comparing the simulated and measured results, which are in good agreement.