James Myers

8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications

The Internet of Things is widely expected to comprise billions of connected devices, many of which will be wireless sensor nodes (WSN). One challenge this poses is energy efficiency, as it will prove cost-prohibitive to regularly replace billions of batteries. Node cost is another concern, which will demand ever-greater integration. Ease of SW development must also remain a priority to HW designers. Addressing all of the above, this paper presents an 11.7pJ/cycle subthreshold WSN processing sub-system implemented in low-leakage 65nm CMOS, scalable from 850nW active power at 250mV to 66MHz at 900mV, with a fully integrated 82% peak-efficiency voltage regulator for direct-battery operation, and supporting 80nW CPU and RAM state-retention power gating for SW-transparent leakage reduction.

A Subthreshold ARM Cortex-M0+ Subsystem in 65 nm CMOS for WSN Applications with 14 Power Domains, 10T SRAM, and Integrated Voltage Regulator

The Internet of Things (IoT) is widely predicted to comprise billions of connected devices, many of which will be wireless sensor nodes (WSN). Energy efficiency is a huge challenge here, followed by node cost and ease of software (SW) development. Addressing all of the above, this paper presents an 11.7 pJ/cycle subthreshold ARM Cortex-M0+ WSN processing subsystem implemented in low-leakage 65 nm CMOS. Voltage and frequency scalability is from 850 nW active power at 250 mV to 66 MHz above 900 mV, with a fully integrated 82% peak-efficiency voltage regulator for direct-battery operation, and supporting 80 nW CPU and RAM state-retention power gating for SW transparent leakage reduction. SW and system optimization approaches are described and a 2.94 μW SW ECG workload is presented.

Active Mode Subclock Power Gating

This paper presents a technique, called subclock power gating, for reducing leakage power during the active mode in low performance, energy-constrained applications. The proposed technique achieves power reduction through two mechanisms: 1) power gating the combinational logic within the clock period (subclock) and 2) reducing the virtual supply to less than Vth rather than shutting down completely as is the case in conventional power gating. To achieve this reduced voltage, a pair of nMOS and pMOS transistors are used at the head and foot of the power gated logic for symmetric virtual rail clamping of the power and ground supplies. The subclock power gating technique has been validated by incorporating it with an ARM Cortex-M0 microprocessor, which was fabricated in a 65-nm process. Two sets of experiments are done: the first experimentally validates the functionality of the proposed technique in the fabricated test chip and the second investigates the utility of the proposed technique in example applications. Measured results from the fabricated chip show 27% power saving during the active mode for an example wireless sensor node application when compared with the same microprocessor without subclock power gating.

Photovoltaic Cells for Micro-Scale Wireless Sensor Nodes: Measurement and Modeling to Assist System Design

Energy harvesting enables perpetual operation of wireless sensor nodes by scavenging energy from the environment. Light energy harvesting using photovoltaic (PV) cells is preferred as they offer the highest volumetric power output allowing nodes to be as small as possible. However, their power output can be spatially and temporally-variable. This work investigates the performance of cm2-scale photovoltaic (PV) cells, and reports on a new measurement and characterization platform. Results show that micro photovoltaic (PV) cells perform differently from large panels: power is not simply a function of area and light levels, and manufacturing variability can be a major issue. The method presented enables the rational design of micro-scale systems, including their maximum power point tracking circuits, and the evaluation of techniques for energy-neutrality (such as workload throttling) at design-time.

Clock-modulation based watermark for protection of embedded processors

This paper presents a novel watermark generation technique for the protection of embedded processors. In previous work, a load circuit is used to generate detectable watermark patterns in the ASIC power supply. This approach leads to hardware area overheads. We propose removing the dedicated load circuit entirely, instead to compensate the reduced power consumption the watermark power pattern is emulated by reusing existing clock gated sequential logic as a zero-overhead load circuit and modulating the clock-gating enable signal with the watermark sequence. The proposed technique has been validated through experiments using two ASICs in 65nm CMOS, one with an ARM Cortex-M0 microcontroller and one with a Cortex-A5 microprocessor. Silicon measurement results verify the viability of the technique for embedded processors. Furthermore, the proposed clock modulation technique demonstrates a significant area reduction, without compromising the detection performance. In our experiments an area overhead reduction of 98% was achieved. Through reuse of existing logic and reduction of watermark hardware implementation costs, the proposed clock modulation technique offers an improved robustness against removal attacks.

Energy Neutral Sensor System With Micro-scale Photovoltaic and Thermoelectric Energy Harvesting

Minimizing power conversion losses is critical for energy neutral operation of micro-scale energy harvested sensor nodes. These small form-factor sensor nodes rely on miniature harvesters with low output voltages that must be boosted with large conversion ratios to recharge batteries or super-capacitors. Selective Direct Operation (SDO), a technique to selectively avoid power conversion and thereby eliminate conversion loss in energy harvested systems has been demonstrated as an effective technique for light harvesters. This paper extends SDO to thermoelectric generators (TEGs). SDO exploits the ultra-low circuit functional voltages, enabling sensor systems to effectively harvest energy from cm-scale TEGs which output few 10s of mW but at low output voltages (100s of mV). PV cell construction from prior-work, TEG characterization and field measurements are presented in this paper to demonstrate the effectiveness of SDO and co-designing energy harvesters, power conversion circuits and digital sub-systems.

Unconventional Layout Techniques for a High Performance, Low Variability Subthreshold Standard Cell Library

A novel subthreshold sizing strategy utilizing the Inverse Narrow Width Effect is demonstrated that has the largest range of propagation delays within the same cell footprint and lowest variability of any subthreshold sizing strategy thus far proposed. Simulation results and ring oscillators implemented in a commercial 65nm low power process confirm a propagation delay improvement of up to 1.95X over the standard superthreshold sizing strategy at 300mV and below. 32 bit multipliers are then synthesized and static timing analysis performed at several subthreshold voltage corners to illustrate applicability to real designs in conventional EDA design flows.

Integrated Reciprocal Conversion With Selective Direct Operation for Energy Harvesting Systems

Energy harvesting IoT systems aim for energy neutrality, i.e., harvesting at least as much energy as is needed. This, however, is complicated by variations in environmental energy and application demands. Conventional systems use separate power converters to interface between the harvester and the storage, and then to the CPU system. Reciprocal power conversion has recently been proposed to perform both roles, eliminating redundancy and minimizing losses. This paper proposes to enhance this topology with “selective direct operation,” which completely bypasses the converter when appropriate. The integrated system, with 82% bidirectional conversion efficiency, was validated in 65-nm CMOS with only the harvester, battery, and decoupling capacitors being off-chip. Optimized for operation with cm2 photo-voltaic cell and a 32-b sub-threshold processor, the scheme enables up to 16% otherwise wasted energy to be utilized to provide >30% additional compute cycles under realistic indoor lighting conditions. Measured results show 84% peak conversion efficiency and energy neutral execution of benchmark sensor software (ULPBench) with cold-start capability.

Design challenges for near and sub-threshold operation: A case study with an ARM Cortex-M0+ based WSN subsystem

Energy-efficient, low-cost wireless sensor nodes (WSN) will be a key component in enabling the Internet of Things. The main challenges for these nodes are energy efficiency, cost and ease of software development. At ARM Research, we investigate sub-threshold and near-threshold systems using a custom-built 65nm CMOS ARM Cortex-M0+ platform. This paper will present key challenges of implementing an ultra-low-voltage SoC, managing leakage and dynamic power, and scaling operating voltage from full voltage to sub-threshold operation. We will cover the design of custom voltage regulator and SRAM IP blocks and also consider a real-world ECG signal processing application.

A 12.4pJ/cycle sub-threshold, 16pJ/cycle near-threshold ARM Cortex-M0+ MCU with autonomous SRPG/DVFS and temperature tracking clocks

IoT requirements are almost as varied as the Things to which they are applied, but common demands are maximum battery life with minimum system cost and physical volume. Sub-threshold operation is promising, but even a single un-optimized or always-on component can eliminate low-voltage gains elsewhere. This work presents a highly integrated sub-threshold capable ARM based MCU with fully integrated multi-mode IVR, always-on power control, and on-chip clock sources, achieving 12.44pJ/cycle active energy (6.3pJ/cycle ideal), 139.4nW standby power (46nW ideal) and 1μW ULPBench power. Simple adaptive circuits are demonstrated to be efficient and correct for standby IVR and active system clocks across 0–70°C.