James P. Shiely

Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography

Self-aligned double patterning (SADP) lithography is a leading technology for 10nm node Metal layer fabrication. In order to achieve successful decomposition, SADP-compliant design becomes a necessity. Spacer-Is-Dielectric (SID) is the most popular flavor of SADP with higher flexibility in design. This paper makes a careful study on the challenges for SID-compliant detailed routing and proposes a graph model to capture the decomposition violations and SID intrinsic residue issues. Then a negotiated congestion based scheme is adopted to solve the overall routing problem. The proposed SID-compliant detailed routing algorithm simultaneously assigns colors to the routed wires, which provides valuable information guiding SID decomposition. In addition, if one pin has multiple candidate locations, the optimal one will be automatically determined during detailed routing. The decomposability of the conflict-free routing layers produced by our detailed router is verified by a commercial SADP decomposition tool.

OPC strategies to minimize mask cost and writing time

As k1 factors decline, optical proximity correction (OPC) treatments required to maintain dimensional tolerances involve increasingly complex correction shapes. This translates to more detailed, larger mask pattern databases. Intricate, dense mask-layouts increase mask writing time and cost. OPC employment within a growing number of lithography layers compounds the issue, leading to skyrocketing mask-set costs and long turn-times. ASIC manufacturing, where average chip life cycles consume less than 500 wafers, is particularly hard hit by elevated mask manufacturing costs. OPC increases mask data mainly by adding geometric detail - serifs, hammerheads, jogs, etc - to the design layout. The vertex count, a measure of shape complexity, typically expands by a factor of 2 to 5, depending on OPC objectives and accuracy requirements. OPC can also increase hierarchic data file size through loss of hierarchic compression. In this paper we outline several alternatives for reducing OPC data base size and for making OPC layout configurations friendlier to mask fabrication tools. An underlying assumption is that there is an optimum OPC treatment dictated by the behavior of the process, and that approximations to this ideal involve trade-offs with OPC accuracy. To whatever extent OPC effectiveness can be maintained while accuracy is compromised, mask complexity can be reduced.

Shadowing effect modeling and compensation for EUV lithography

Extreme ultraviolet (EUV) lithography is one of the leading technologies for 16nm and smaller node device patterning. One patterning issue intrinsic to EUV lithography is the shadowing effect due to oblique illumination at the mask and mask absorber thickness. This effect can cause CD errors up to a few nanometers, consequently needs to be accounted for in OPC modeling and compensated accordingly in mask synthesis. Because of the dependence on the reticle field coordinates, shadowing effect is very different from the traditional optical and resist effects. It poses challenges to modeling, compensation, and verification that were not encountered in tradition optical lithography mask synthesis. In this paper, we present a systematic approach for shadowing effect modeling and model-based shadowing compensation. Edge based shadowing effect calculation with reticle and scan information is presented. Model calibration and mask synthesis flows are described. Numerical experiments are performed to demonstrate the effectiveness of the approach.

Approximation of three dimensional mask effects with two dimensional features

As an important resolution enhancement technique (RET), alternating aperture phase shift masks (AAPSM) has been widely adopted in 90 nm technology node and beyond. Mask topographical effect due to the 3D nature of the shifter features is becoming an increasingly important factor in lithography modeling. Rigorous 3D modeling of PSM is very computationally demanding thus impractical for full chip optical proximity correction (OPC). Here we introduce an alternative approach employing boundary layers to effectively approximate the 3D mask effect. We will present the model calibration versus real wafer data using the boundary layers and the corresponding OPC correction flow.

Advanced model formulations for optical and process proximity correction

As post-litho process effects account for a larger and larger portion of CD error budgets, process simulation terms must be given more weight in the models used for proximity correction. It is well known that for sub-90 nm processes resist and etch effects can no longer be treated as a small perturbation on a purely optical (aerial image) OPC model. The aerial image portion of the model must be combined in a more appropriate way with empirical terms describing resist and etch effects. The OPC engineer must choose a model form which links an optical component with a resist/etch component in a manner that balances efficiency, robustness and fidelity to the aerial image, among other factors. No single way of connecting litho and etch models is ideal in all cases; the best form of linkage depends on the particular litho and etch process to be simulated. In this paper, we provide practical guidelines for linking litho and etch components of a model, using a representative 70 nm process with a large etch bias as an example. This 70 nm case study, which is representative of many sub-90 nm processes that rely on etch to shrink critical features, presents special challenges for OPC modeling. For the process under study, lines were are printed in resist at 120 nm, and the litho model was verified via resist SEM measurements taken at the resist edge. Note that a thresholded aerial image is not well-characterized a distance 25 nm from the resist edge. This is roughly the distance the edge moves back due to the etch step. Although in some cases etch bias can be calculated from aerial image contrast, in general etch bias cannot be predicted from the aerial image because litho and etch are governed by different underlying physics. The model forms available for linking litho and etch range from the efficient “lumped” form, which combines litho and etch simulation in a single model, to a highly accurate two-stage form which separates the two components. In this paper we evaluate the following model forms for applicability to the 70 nm process under study: 1) Aerial image/load kernel combined (“lumped”) model form 2) Aerial image/rule offset “hybrid” model form 3) Separate litho and etch models (2-stage correction)

Combining lithography and etch models in OPC modeling

With constant shrinking of device critical dimensions (CD), the quality of pattern transfer in IC fabrication depends on the etch process and the exposure process fidelities, and the interaction of lithographic and etching processes is no longer negligible. Etch effect correction with accurate models has become an important component in optical proximity correction (OPC) modeling and related applications. It is now commonly accepted that the lithographic and etch effects should be modeled and corrected in a sequential and staged way: a resist (or lithographic) model should be created and used for lithographic effect compensation, and an etch model should be created and used for etch effect compensation. However, there can be various degrees of separation of these two modeling stages. In order to optimally capture the significant variation in the post-development resist patterns and post-etching patterns, it is helpful to integrate these two processes together for the OPC model calibration practice. In this paper, we analyze the integrated simulation approach in OPC modeling where the entire resist model information is made fully accessible in the etch modeling stage to allow the possibility of resist and etch co-optimization, e.g. through adjusting the resist model to optimally fit the etch data. Furthermore, the integrated simulation technique is integrated into a verification flow to simplify the conventional staged flow.

Etch modeling for accurate full-chip process proximity correction

The challenges of the 65 nm node and beyond require new formulations of the compact convolution models used in OPC. In addition to simulating more optical and resist effects, these models must accommodate pattern distortions due to etch which can no longer be treated as small perturbations on photo-lithographic effects. (Methods for combining optical and process modules while optimizing the speed/accuracy tradeoff were described in “Advanced Model Formulations for Optical and Process Proximity Correction”, D. Beale et al, SPIE 2004.) In this paper, we evaluate new physics-based etch model formulations that differ from the convolution-based process models used previously. The new models are expressed within the compact modeling framework described by J. Stirniman et al. in SPIE, vol. 3051, p469, 1997, and thus can be used for high-speed process simulation during full-chip OPC.

Simulations of immersion lithography

Immersion lithography has been regarded as the most viable contender to extend the resolution capability of optical lithography using 193nm wavelength. In parallel with the tremendous effort of overcoming the engineering challenges in immersion, support from modeling and simulations is strongly needed. Although immersion simulation has become available through a number of simulation tools, we need to investigate the model generation and its compatibility within the context of full-chip optical proximity correction (OPC). In this paper, we will describe the physics of a full vector model that is necessary for the high NA optical modeling under immersion. In this full vector model, we consider not only the plane wave decomposition as light travels from the mask to wafer plane, but also the refraction, transmission and reflection of light through a thin film stack on the wafer. We integrated this comprehensive vector model into Synopsys OPC modeling tool ProGen. Through ProGen simulation results, we will discuss several important merits of immersion lithography, as well as the full portability of immersion models into OPC process flow.

Use of optical defocus components to investigate and improve pattern spatial frequency characteristics for more robust layouts

As semiconductor manufacturing moves to smaller geometries, the existing methodologies for verifying the manufacturability of a design are increasingly cumbersome. Current practice is to use geometric “design rules”—such as minimum spacing and width constraints—to identify design configurations that are not manufacturable or likely to reduce yield. One manufacturing property that is particularly difficult to capture accurately with geometric rules is the robustness of the layout configuration with respect to variation through the lithographic process window. The nonlinear characteristics of optical partial coherence effects, particularly strong in modern exposure systems with off-axis illumination, are currently incorporated into the design rules through an exhaustive empirical process. The resulting design rules can be overly conservative to insure complete problem pattern capture, and this may result in unnecessary restrictions on the design that reduce the layout density or interfere with circuit perfo...

Fast synthesis of topographic mask effects based on rigorous solutions

Topographic mask effects can no longer be ignored at technology nodes of 45 nm, 32 nm and beyond. As feature sizes become comparable to the mask topographic dimensions and the exposure wavelength, the popular thin mask model breaks down, because the mask transmission no longer follows the layout. A reliable mask transmission function has to be derived from Maxwell equations. Unfortunately, rigorous solutions of Maxwell equations are only manageable for limited field sizes, but impractical for full-chip optical proximity corrections (OPC) due to the prohibitive runtime. Approximation algorithms are in demand to achieve a balance between acceptable computation time and tolerable errors. In this paper, a fast algorithm is proposed and demonstrated to model topographic mask effects for OPC applications. The ProGen Topographic Mask (POTOMAC) model synthesizes the mask transmission functions out of small-sized Maxwell solutions from a finite-difference-in-time-domain (FDTD) engine, an industry leading rigorous simulator of topographic mask effect from SOLID-E. The integral framework presents a seamless solution to the end user. Preliminary results indicate the overhead introduced by POTOMAC is contained within the same order of magnitude in comparison to the thin mask approach.