Daniel F. Beale

Advanced model formulations for optical and process proximity correction

As post-litho process effects account for a larger and larger portion of CD error budgets, process simulation terms must be given more weight in the models used for proximity correction. It is well known that for sub-90 nm processes resist and etch effects can no longer be treated as a small perturbation on a purely optical (aerial image) OPC model. The aerial image portion of the model must be combined in a more appropriate way with empirical terms describing resist and etch effects. The OPC engineer must choose a model form which links an optical component with a resist/etch component in a manner that balances efficiency, robustness and fidelity to the aerial image, among other factors. No single way of connecting litho and etch models is ideal in all cases; the best form of linkage depends on the particular litho and etch process to be simulated. In this paper, we provide practical guidelines for linking litho and etch components of a model, using a representative 70 nm process with a large etch bias as an example. This 70 nm case study, which is representative of many sub-90 nm processes that rely on etch to shrink critical features, presents special challenges for OPC modeling. For the process under study, lines were are printed in resist at 120 nm, and the litho model was verified via resist SEM measurements taken at the resist edge. Note that a thresholded aerial image is not well-characterized a distance 25 nm from the resist edge. This is roughly the distance the edge moves back due to the etch step. Although in some cases etch bias can be calculated from aerial image contrast, in general etch bias cannot be predicted from the aerial image because litho and etch are governed by different underlying physics. The model forms available for linking litho and etch range from the efficient “lumped” form, which combines litho and etch simulation in a single model, to a highly accurate two-stage form which separates the two components. In this paper we evaluate the following model forms for applicability to the 70 nm process under study: 1) Aerial image/load kernel combined (“lumped”) model form 2) Aerial image/rule offset “hybrid” model form 3) Separate litho and etch models (2-stage correction)

Enriching design intent for optimal OPC and RET

In typical rule- or model-based optical proximity correction (OPC) the goal is to align the silicon layout edges as closely as possible to the corresponding edges in the design layout. OPC precision requirements are approaching 1nm or less at the 0.1mm process node. While state-of-the-art OPC tools are capable of operating at this accuracy, such tight requirements increase computational cycle time, output file size, and photomask fabrication cost. Accuracy requirements on different features in the design may vary widely, and regions that do not need the highest accuracy can be exploited to reduce OPC complexity. For example, transistor gate dimensions require tighter dimensional control than interconnect features on the polysilicon layer. Furthermore gate features typically occupy less area than interconnect. When relaxed OPC accuracy requirements are applied to the interconnect features, but not the gate features, the overall complexity of the polysilicon mask pattern can be significantly reduced without losing accuracy where it counts.

Etch modeling for accurate full-chip process proximity correction

The challenges of the 65 nm node and beyond require new formulations of the compact convolution models used in OPC. In addition to simulating more optical and resist effects, these models must accommodate pattern distortions due to etch which can no longer be treated as small perturbations on photo-lithographic effects. (Methods for combining optical and process modules while optimizing the speed/accuracy tradeoff were described in “Advanced Model Formulations for Optical and Process Proximity Correction”, D. Beale et al, SPIE 2004.) In this paper, we evaluate new physics-based etch model formulations that differ from the convolution-based process models used previously. The new models are expressed within the compact modeling framework described by J. Stirniman et al. in SPIE, vol. 3051, p469, 1997, and thus can be used for high-speed process simulation during full-chip OPC.

Etch modeling in RET synthesis and verification flow

The challenges of the 65 nm node and beyond require new formulations of the compact convolution models used in OPC. In addition to simulating more optical and resist effects, these models must accommodate pattern distortions due to etch which can no longer be treated as small perturbations on photo-lithographic effects. (Methods for combining optical and process modules while optimizing the speed/accuracy tradeoff were described in “Advanced Model Formulations for Optical and Process Proximity Correction”, D. Beale et al, SPIE 2004.) In this paper, we evaluate new physics-based etch model formulations that differ from the convolution-based process models used previously. The new models are expressed within the compact modeling framework described by J. Stirniman et al. in SPIE, vol. 3051, p469, 1997, and thus can be used for high-speed process simulation during full-chip OPC.

Multi-layer model vs. single-layer model for N and P doped poly layers in etch bias modeling

In modern photolithography, ever smaller critical dimension (CD) budgets require tighter control over the entire process, demanding more accurate practice of optical proximity correction (OPC). In last decade, the model based OPC (MBOPC) has outpaced the rule based OPC (RBOPC) and become widely adopted in semiconductor industry. During the MBOPC process, the physical models are called to compute the signal values at the evaluation points and the design patterns are perturbed such that the final model contours are as close to the targets as possible. It has been demonstrated that in addition to simulating the optics and resist effects, the physical models must accommodate the pattern distortion due to etch process as well. While the etch process may be lumped with optics and resist processes into one model for the 65nm and above nodes, it can no longer be treated as small perturbations on photolithographic effects for more advanced nodes and it is highly desired to build a physics-based etch model formulations that differ from the conventional convolution-based process models used to simulate the optical and resist effect. Our previous studies proposed a novel non-linear etch modeling object in combination with conventional convolution kernels, which simulates the non-optics and non-resist proximity effect successfully. This study examines further the non-linear etch modeling method by checking the different behaviors of N and p doped layers which physically have different etching rates and should be represented differently in etch modeling. The experimental results indicate that the fitting accuracy is significantly improved when the data points are split into N and P groups and calibrated separately. The N and P layer etch models are used in staged MBOPCs and the results are compared with single-layer model as well.

Etch analysis of patterns to comprehend manufacturability

Negative etch bias is often used to decrease the minimum linewidth beyond what is possible with lithography alone, for example 110 nm minimum CD in resist and 70 nm minimum CD after etch. If the minimum space that can be opened in resist is, for example, 30 nm a true 70 nm half-pitch can be achieved when an etch shrink is employed. Due to iso-dense bias and other proximity effects, however, positive etch bias can also occur. This leads to the unfavorable situation where litho must print lines in resist smaller than the lines in the final post-etch silicon. Due to positive etch bias, among other factors, it is possible to create a configuration that can be realized from the point of view of etch, but can not be created due to photolithography or mask constraints. Specific trouble spots include boundary regions which transition between one set of DRC rules and another. With a new highly accurate etch model, problematic configurations can be identified and used to modify the design to make the etch, photolithography, and mask construction processes realizable. This paper will demonstrate unrealizable pattern conditions that can be found using a non-linear etch model for OPC[R], leading to layout configuration changes which improve the mask construction and photolithography processes.

Mask process effect aware OPC modeling

Although the mask pattern created by fine ebeam writing is four times larger than the wafer pattern, the mask proximity effect from ebeam scattering and etch is not negligible. This mask proximity effect causes mask-CD errors and consequently wafer-CD errors after the lithographic process. It is therefore necessary to include the mask proximity effect in optical proximity correction (OPC). Without this, an OPC model can not predict the entire lithography process correctly even using advanced optical and resist models. In order to compensate for the mask proximity effect within OPC a special model is required along with changes to the OPC flow. This article presents a method for producing such a model and OPC flow and shows the difference in results when they are used.

Programmable RET Mask Layout Verification

Emerging resolution enhancement techniques (RET) and OPC are dramatically increasing the complexity of mask layouts and, in turn, mask verification. Mask shapes needed to achieve required results on the wafer diverge significantly from corresponding shapes in the physical design, and in some cases a single chip layer may be decomposed into two masks used in multiple exposures. The mask verification challenge is to certify that a RET-synthesized mask layout will produce an acceptable facsimile of the design intent expressed in the design layout. Furthermore costs, tradeoffs between mask-complexity, design intent, targeted process latitude, and other factors are playing a growing role in helping to control rising mask costs. All of these considerations must in turn be incorporated into the mask layout verification strategy needed for data prep sign-off. In this paper we describe a technique for assessing the lithographic quality of mask layouts for diverse RET methods while effectively accommodating various manufacturing objectives and specifications. It leverages the familiar DRC paradigm for identifying errors and producing DRC-like error shapes in its output layout. It integrates a unique concept of “check figures” - layer-based geometries that dictate where and how simulations of shapes on the wafer are to be compared to the original desired layout. We will show how this provides a highly programmable environment that makes it possible to engage in “compound” check strategies that vary based on design intent and adaptive simulation with multiple checks. Verification may be applied at the “go/no go” level or can be used to build a body of data for quantitative analysis of lithographic behavior at multiple process conditions or for specific user-defined critical features. In addition, we will outline automated methods that guide the selection of input parameters controlling specific verification strategies.