James S. Caravella

A low voltage SRAM for embedded applications

A 4-kb SRAM design is presented with functionality of 12 MHz at a supply voltage of 0.9 V with an r.m.s. run power (1 MHz) of 18 /spl mu/W. The circuit operates at maximum frequency of 40 MHz at a supply voltage of 1.6 V with an rms run power (1 MHz) of 64 /spl mu/W. The design utilizes a subblocked array architecture as well as selective use of NOR/NAND-based decode logic. The sense amplifier design is a low voltage, glitch-free design to conserve power.

Current mode transceiver logic, (CMTL) for reduced swing CMOS, chip to chip communication

A reduced voltage swing CMOS interface for differential and single-ended signaling is presented. Differential 400-MHz transmitter/receiver operation with a 5-V supply and 300-MHz operation with a 3.3-V supply are both shown. Results showing PECL (positive ECL) compatibility are also presented.<<ETX>>

Three volt to five volt CMOS interface circuit device leakage limited DC power dissipation

A CMOS interface circuit from three to five volts is presented in which DC power consumption is defined by a single transistors OFF leakage current. The interface design provides signal level translation while minimizing propagation delay and power dissipation. Typical propagation delays are on the order of 1.5 ns, with DC power dissipation less than 1 pW. The primary application of the interface is mixed voltage gate arrays with a 3.3-V core and 5.0-V I/Os.<<ETX>>

Circuit techniques for standby mode/Iddq test compatible voltage comparators

This paper describes the means for IDDQ (quiescent supply current) testing of digital and mixed signal systems that contain analog circuits. A simple comparator design is presented that has been modified to be IDDQ test compatible. A by product of IDDQ test compatibility is a standby state that allows for a significant reduction in the IDDQ of the circuit, and an output data retention capability.