Andreas A. Wild

A Qualitative Study on Optimized MOSFET Doping Profiles

We present the two-dimensional optimization of the acceptor doping profile of a 0.25 µm MOSFET which improves the drive current by 48% compared to a uniformly doped device delivering the same drain-source leakage current. Various values for the supply voltage and the allowed leakage current are used to qualitatively investigate their influence on the optimal profile.

Drive performance of an asymmetric MOSFET structure: the peak device

The drive performance of a new MOSFET structure, the peak device, resulting from recent doping profile optimizations of a 0.25 μm n-MOSFET for 1.5 V supply voltage, is investigated. Explanations for the improved performance are given using two-dimensional device simulation. With an analytical transistor model fitted to the two-dimensional device characteristics, the relevant physical effects are identified. It is shown that the superior drive performance of the peak device can mainly be addressed to the reduction of the effective gate length and the improved bulk effect.

Systematic calibration of process simulators for predictive TCAD

This paper demonstrates a methodology for systematic calibration of models in process simulators and its impact on improvement of accuracy and predictive capability of a TCAD system. A software tool for calibration with numerical optimization has been developed and used to calibrate a transient enhanced diffusion (TED) model under low-dose implantation conditions. Using the calibrated model, predictive simulations were performed prior to SIMS measurements. The systematic calibration and its validation through independent experiments showed significantly improved accuracy and predictive capability of process and device simulation system.

Electromigration on oxide steps

Abstract A test vehicle has been used to investigate the influence of the oxide steps on electromigration. An automated test setup allowed precise determination of the time to failure. The experiments showed that the time-to-failure is influenced by the surface topography at high current densities. One metal strip interrupted by electromigration recovered during the SEM voltage contrast investigation.

Modern trends in ASIC: Mixing technologies

Abstract ASICs are about to become one of the dominant products of the electronic industry, determining the progress of specific technologies. This paper describes recent developments in manufacturing, design and software driven by ASICs. Under the pressure of continuously increasing integration levels, the possibility of integrating systems on a chip is closer. In response to system needs, the common characteristic of the ASIC trends is the capability to mix different technologies on a single chip.

Modeling metastable states in ASIC

Abstract The metastable behavior is unavoidable in sequential circuits. It is therefore important to characterize the circuit elements with this respect. The response time method correlates the additional delay due to the onset of metastability with the MTBF; it has been used to determine the failure window of MOSAIC3 flip-flops (emitter width 1μm, transition frequency 15GHz). The double sampling method allows a more accurate investigation of the metastability conditions. It has been applied to HDC gate arrays (CMOS, 1μm drawn channel length). Based upon the experimental results, a simulation model has been introduced in the ASIC library.

Toward high-level synthesis for ASIC design

Abstract High-level synthesis is a design style that considerably increases design productivity, resulting in correct-by-construction optimized structures. Yet, to be efficient, the top-down design has to be complemented with knowledge about the ‘cost’ of its detailed implementation (timing, size, power dissipation etc.). The efficient use of the synthesis tools at their current stage requires careful (manual) modelling. Also, essential elements of the design are not covered by the high-level descriptions and tools but are taken into account at a late stage of the project, typically in post-processing.

Accurate delay models for ECL logic synthesis

The usage of logic synthesis tools for ECL logic has been questionable, among other reasons, because of the discrepancy between the simple, computationally efficient models required by synthesis and the more and more sophisticated models required for accurate simulation. The paper demonstrates that with appropriate choice of modelling parameters, it is possible to map an existing ECL simulation library to a synthesis library with errors below 1%. The authors review the basic delay calculation algorithms provided by a prominent commercial ECL Logic Synthesis tool (Synopsys). They show how delay data is generated by their proprietary delay calculator DECAL. They develop a simplification scheme that enables the algorithms given in Synopsys to produce accurate results. Finally, they present some results on accuracy.<<ETX>>

The impact of the interconnect delays on a high performance asic array

Abstract The importance of the interconnect delays in modern ICs increases since they do not scale proportionally with device delays. This paper presents the main aspects of the ASIC design and development which are influenced by the shift in the time budget of an ASIC due to the metal-delays weight, using a high performance array in a 0.6 μm BiCMOS process as an example.