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Dive into the research topics where James W. Dawson is active.

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Featured researches published by James W. Dawson.


design automation conference | 2004

Design and implementation of the POWER5 microprocessor

Joachim Gerhard Clabes; Joshua Friedrich; Mark Sweet; Jack DiLullo; Sam Gat-Shang Chu; Donald W. Plass; James W. Dawson; Paul Muench; Larry Powell; Michael Stephen Floyd; Balaram Sinharoy; Mike Lee; Michael Normand Goulet; James Donald Wagoner; Nicole S. Schwartz; Stephen Larry Runyon; Gary Gorman; Phillip J. Restle; Ronald Nick Kalla; Joseph McGill; J. Steve Dodson

POWERS offers significantly increased performance over previous POWER designs by incorporating simultaneous multithreading, an enhanced memory subsystem, and extensive RAS and power management support. The 276M transistor processor is implemented in 13Onm silicon-on-insulator technology with 8-level of Cu metallization and operates at >1.5 GHz


Archive | 1992

Module level electronic redundancy

Robert Dean Adams; Henry A. Bonges; James W. Dawson; Erik L. Hedberg


Archive | 1988

Memory cell and read circuit

James W. Dawson; Panagiotis Andrew Phillips


Archive | 1991

Latch assisted fuse testing for customized integrated circuits

James W. Dawson; George A. DeLuca; Michael Nicewicz


Archive | 2005

Method and apparatus for implementing multiple column redundancy for memory

James W. Dawson; Thomas J. Knips; Donald W. Plass; Kenneth J. Reyer


Archive | 2002

SOI cell stability test method

James W. Dawson; Paul A. Bunce; Donald W. Plass


Archive | 2011

SYSTEMS AND METHODS FOR MEMORY DEVICE PRECHARGING

James W. Dawson; Rajiv V. Joshi; Noam Jungmann; Elazar Kachir; Rouwaida Kanj; Ehud Nir; Donald W. Plass


Archive | 2005

ABIST data compression and serialization for memory built-in self test of SRAM with redundancy

James W. Dawson; Thomas J. Knips; Donald W. Plass; Kenneth J. Reyer


Archive | 2003

Non-binary address generation for ABIST

Thomas J. Knips; Tom Y. Chang; James W. Dawson; Douglas J. Malone


Archive | 2005

GLOBAL AND LOCAL READ CONTROL SYNCHRONIZATION METHOD AND SYSTEM FOR A MEMORY ARRAY CONFIGURED WITH MULTIPLE MEMORY SUBARRAYS

Paul A. Bunce; John D. Davis; James W. Dawson; Donald W. Plass

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