Paul A. Bunce

Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System

This paper describes the circuit and physical design features of the z196 processor chip, implemented in a 45 nm SOI technology. The chip contains 4 super-scalar, out-of-order processor cores, running at 5.2 GHz, on a die with an area of 512 mm2 containing an estimated 1.4 billion transistors. The core and chip design methodology and specific design features are presented, focusing on techniques used to enable high-frequency operation. In addition, chip power, IR drop, and supply noise are discussed, being key design focus areas. The chips ground-breaking RAS features are also described, engineered for maximum reliability and system stability.

A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor

A dual-read 8-way set-associative data cache comprising four 16kB SRAMs and 2 set-prediction macros per P0WER6 core is presented. The array utilizes a 0.75mum2 butted-junction split-word line 6T cell in 65nm SOI. The design features dual power supplies, unidirectional polysilicon, and hierarchical undamped bit lines for enhanced cell stability and performance

7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor

The L1 cache for the 5.5 GHz 32nm zEnterprise™ EC12 processor requires SRAM designs that make aggressive use of dynamic circuitry. As technology has scaled and transistor counts have grown, random device variability [1] and power limitations have become significant challenges. In particular, random device-variability-induced pulse shrinkage and misalignment in dynamic signals must be carefully addressed. Described here are a series of new design approaches enabling L1 cache SRAM operation at 7GHz, including a 3-level bitline hierarchy, decreased dynamic path lengths, localized read enables, and a power-savings mechanism in which selective columns can be partially powered down.