Kenneth J. Reyer

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access

A 1.1 Mb embedded DRAM macro (eDRAM), for next-generation IBM SOI processors, employs 14 nm FinFET logic technology with 0.0174 μm2 deep-trench capacitor cell. A Gated-feedback sense amplifier enables a high voltage gain of a power-gated inverter at mid-level input voltage, while supporting 66 cells per local bit-line. A dynamic-and-gate-thin-oxide word-line driver that tracks standard logic process variation improves the eDRAM array performance with reduced area. The 1.1 Mb macro composed of 8 ×2 72 Kb subarrays is organized with a center interface block architecture, allowing 1 ns access latency and 1 ns bank interleaving operation using two banks, each having 2 ns random access cycle. 5 GHz operation has been demonstrated in a system prototype, which includes 6 instances of 1.1 Mb eDRAM macros, integrated with an array-built-in-self-test engine, phase-locked loop (PLL), and word-line high and word-line low voltage generators. The advantage of the 14 nm FinFET array over the 22 nm array was confirmed using direct tester control of the 1.1 Mb eDRAM macros integrated in 16 Mb inline monitor.

17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access

IBM introduced trench capacitor eDRAM into its high performance microprocessors beginning with 45nm and Power 7 [1] to provide a higher density cache without chip crossings. Whereas the 45 and 32nm designs employ a micro sense amplifier [2] and three-level bitline hierarchy, the design implemented for 22nm utilizes a higher gain sense amplifier and two-level bitline architecture that together provide significant reductions in area, latency, and power. This 22nm design style has been migrated into a 14nm FinFET [3] learning vehicle, complete with an ABIST engine, wordline charge pumps (VPP and VWL), and padcage interface circuitry.