Massimo Brandolini

Second-order intermodulation mechanisms in CMOS downconverters

An in-depth analysis of the mechanisms responsible for second-order intermodulation distortion in CMOS active downconverters is proposed in this paper. The achievable second-order input intercept point (IIP2) has a fundamental limit due to nonlinearity and mismatches in the switching stage and improves with technology scaling. Second-order intermodulation products generated by the input transconductor or due to self-mixing usually contribute to determine the IIP2 even though they can, at least in principle, be eliminated. The parasitic capacitance loading the switching-stage common source plays a key role in the intermodulation mechanisms. Moreover, the paper shows that, besides direct conversion and low intermediate frequency (IF), even superheterodyne receivers can suffer from second-order intermodulation if the IF is not carefully chosen. The test vehicle to validate the proposed analysis is a highly linear 0.18-/spl mu/m direct-conversion CMOS mixer, embedded in a fully integrated receiver, realized for Universal Mobile Telecommunications System applications.

A 0.13 /spl mu/m CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier

This paper presents a fully integrated CMOS receiver front-end based on a direct conversion architecture for UMTS/802.11b-g and a low-IF architecture at 100 kHz for DCS1800. The two key building blocks are a multiband low-noise amplifier (LNA) that uses positive feedback to improve its gain and a highly linear mixer. The front-end, integrated in a 0.13 /spl mu/m CMOS process, exhibits a minimum noise figure of 5.2 dB, a programmable gain that can be varied from 13.5 to 28.5 dB, an IIP3 of more than -7.5 dBm and an IIP2 better than 50 dBm. The total current consumption is 20mA from a 1.2V supply.

A variable gain RF front-end, based on a Voltage-Voltage feedback LNA, for multistandard applications

Employing feedback circuits in RF front-ends can be a key aspect for easy reconfiguration of multistandard receivers. A narrow-band filter can shape the frequency transfer function and, by reflection due to the feedback network, the input impedance. Switching one single filter component thus allows selecting a different standard. We introduce a voltage-voltage feedback low noise amplifier that, besides being easily reconfigurable, shows roughly the same noise and better linearity, for same power consumption, as the conventional inductively degenerated topology. A direct conversion front-end, including the LNA and I and Q mixers, tailored to WLAN applications in the 5-6 GHz range, has been realized in a 0.25-/spl mu/m SiGe BiCMOS process. Prototypes show the following performances: 2.5 dB NF, 31.5 dB gain, -9.5dBm IIP3, and +23dBm minimum IIP2 while consuming 16 mA from a 2.5 V supply.

A +78 dBm IIP2 CMOS direct downconversion mixer for fully integrated UMTS receivers

The demanding dynamic range required by receivers for cell-phone applications makes the design of low-power fully integrated CMOS solutions extremely challenging. Commercially available third-generation (3G) products adopt a hybrid direct conversion architecture, where an inter-stage surface acoustic wave (SAW) filter between low noise amplifier (LNA) and mixer attenuates out-of-band interferers, alleviating linearity requirements set on the downconversion mixer. As a drawback, an off-chip component and an additional LNA are introduced, raising costs. Leveraging an in-depth analysis of second-order inter-modulation mechanisms in active downconversion mixers, this paper presents the design of a 0.18-/spl mu/m CMOS solution with outstanding linearity and noise performances. The input transconductor is RC degenerated, the output resistors are carefully matched and, most important, the parasitic capacitors at switching pair common sources are tuned out. Sixty samples from two distinct fabrication lots have been characterized. Minimum IIP2 is +78 dBm. For comparison, a second solution where inter-modulation products generated by the switching pair are not filtered out has been fabricated and tested. IIP2 values are always lower. Other measured performance results are: 16-dB gain with 4.5-MHz output bandwidth; +10-dBm out-of-band IIP3; 4-nV//spl radic/Hz input referred noise voltage density while drawing 4 mA from 1.8 V.

A 750 mV Fully Integrated Direct Conversion Receiver Front-End for GSM in 90-nm CMOS

The design of RF integrated circuits, at the low voltage allowed by sub-scaled technologies, is particularly challenging in cellular phone applications where the received signal is surrounded by huge interferers, determining an extremely high dynamic range requirement. In-depth investigations of 1/f noise sources and second-order intermodulation distortion mechanisms in direct downconversion mixers have been carried out in the recent past. This paper proposes a fully integrated receiver front-end, including LNA and quadrature mixer, supplied at 750 mV, able to meet GSM specifications. In particular, the direct downconverter employs a feedback loop to minimize second-order common mode intermodulation distortion, generated by a pseudo-differential transconductor, adopted for minimum voltage drop. For maximum dynamic range, the commutating pair is set with an LC filter. Prototypes, realized in a 90-nm RF CMOS process, show the following performances: 51 dBm IIP2, minimum over 25 samples, 1 dB desensitization point due to 3-MHz blocker at -18 dBm, 3.5 dB noise figure (NF), integrated between 1 kHz-100 kHz, 15 kHz 1/f noise corner. The front-end IIP2 has also been characterized with the mixer feedback loop switched off, resulting in an average reduction of 18 dB.

A CMOS direct down-converter with +78dBm minimum IIP2 for 3G cell-phones

A 0.18 /spl mu/m CMOS direct down-converter achieves 78dBm IIP2, 10dBm IIP3, and 4nV//spl radic/Hz noise density. It draws 4mA from a 1.8V supply.

An Embedded 65 nm CMOS Baseband IQ 48 MHz–1 GHz Dual Tuner for DOCSIS 3.0

An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution PLL, and digital image rejection. To our knowledge this is the first reported multichannel broadband tuner embedded in a DOCSIS 3.0 System on a chip implemented in 65 nm pure digital CMOS technology.

An embedded 65 nm CMOS baseband IQ 48 MHz-1 GHz dual tuner for DOCSIS 3.0

An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution phase-locked loop (PLL) and digital image rejection. To our knowledge this is the first reported multi-channel Broadband Tuner embedded in a DOCSIS 3.0 System on a Chip implemented in a 65 nm pure digital CMOS technology.

A 750mV 15kHz 1/f Noise Corner 51dBm IIP2 Direct-Conversion Front-End for GSM in 90nm CMOS

A direct-conversion front-end using a highly linear mixer is implemented in 90nm CMOS. The front-end shows 15kHz 1/f noise corner, 51dBm IIP2, 31.5dB gain, 3.5dB NF, and draws 15mA from 0.75 V

26.6 A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS

The recent emergence of direct sampling in residential broadband satellite and cable receivers has spurred the need for low-power, high-speed (~5GS/s), mid-resolution (~10b) A/D converters. Recently, time-interleaved (TI) SARs have been a popular choice for low-power, medium-speed, mid-resolution ADCs [1-3]. As the conversion rate and resolution requirements increase, TI-SARs become less attractive in terms of power efficiency and complexity compared to TI-pipelined ADCs [4], where the critical SNR, THD, and TI matching are only required in the MDACs resolving the MSBs. In this paper we report a hybrid of TI-pipelined MDAC and TI-SAR, in which the former resolves the 2 MSB bits and the latter resolves the 8 lower bits. This hybrid architecture combines the advantages from each ADC type to achieve better power at 5GS/s. The front-end is implemented by time-interleaving two 2.5b MDAC slices, easing the timing-matching requirement and complexity. The MDAC stage also eases the timing-matching requirement among the TI-SARs by presenting an amplified-and-held signal to each SAR input. This allows taking advantage of a low-resolution SARs simplicity and low power, for the last 8b. This work also proposes a SHA-less front-end to further minimize the ADC power. Two simple calibration techniques are introduced on-chip to enable the topology: (a) an over-range calibration (ORcal) loop to correct the sampling-time error between MDAC and sub-ADC in the SHA-less front-end, and (b) SAR reference calibration to align the SARs full-scale to the MDACs. Figure 26.6.1 shows the timing and functional block diagram of the 5GS/s hybrid SHA-less ADC. The RF buffer directly drives two TI-slices, each comprising a 2.5GS/S MDAC stage to resolve the 2.5 MSB bits, followed by 4-way interleaved 625MS/S SARs to resolve the lower 8b, for a combined 10b resolution (1b overlap), at 5GS/s.