Jan Vaes

3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias

Using standard single damascene type techniques on bulk-Si, combined on one hand with extreme wafer thinning and on the other with Cu-Cu thermo-compression bonding technology, the paper demonstrate yielding 10k through-wafer 3D-via chains with a via pitch of 10μm for a via diameter of 5μm. The bonded contacts exhibit shear strengths exceeding 40MPa. Measurements indicate there is no significant contact resistance at the Cu-Cu bonded interface: within measurement accuracy, the 4-point via chain resistance is consistent with bulk Cu resistivity

3D stacked IC demonstration using a through Silicon Via First approach

We report for the first time the demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of our reference 0.13 mum CMOS process on 200 mm wafers. The top die is thinned down to 25 mum and bonded to the landing wafer by Cu-Cu thermo-compression. Both top and landing wafers contain CMOS finished at M2 to evaluate the process impact both FEOL and BEOL. The results confirm no degradation of the FEOL performance. The functionality of various ring oscillator topologies that include inverters distributed over both top and bottom dies connected through TSVs demonstrates excellent chip integrity after the TSV and 3D stacking process.

The Role of Metal Hydroxides in NiFe Deposition

In this work, the role of hydroxyl compounds during the anomalous NiFe electrodeposition is reinvestigated It is found that the manner in which the boundary conditions are incorporated in existing NiFe models that are based on the chemical equilibrium of species in solution, is not correct and leads to unphysical situations. In order to alleviate this problem, a kinetic description of the homogeneous reactions in the solution is used to calculate the concentration profiles of the ionic species near electrodes. This shows that even the fastest chemical reactions are not in chemical equilibrium in the vicinity of the electrode. Also, the amount of generated hydroxyl ions during proton reduction and hence the extent to which metal ions are hydrolyzed, is far less than assumed in existing models. This result is confirmed experimentally by polarization measurements. It is shown that the Ni-H 2 and Fe-H 2 systems exhibit anomalous codeposition bchavior as well and that inhibition of the Ni and H reduction in the Ni-Fe-H 2 system cannot be explained in terms of metal hydrolysis reactions. Therefore, it is concluded from both the theoretical calculations and the experimental findings, that metal hydrolysis does not play a determining role in anomalous NiFe codeposition.

Highly reliable CMOS-integrated 11MPixel SiGe-based micro-mirror arrays for high-end industrial applications

In this paper we report for the first time on the fabrication of very reliable CMOS-integrated 10 cm2 11 MPixel SiGe-based micro-mirror arrays on top of 6 level metal CMOS wafers. The array, which is to be used as Spatial Light Modulator (SLM) for optical maskless lithography [1,2,3] consists of 8 mum x 8 mum pixels which can be individually addressed by an analog voltage to enable accurate tilt angle modulation. The pixel density is almost double compared to the state-of-the-art [4]. A stable average cupping below 7 nm, an RMS roughness below 1 nm and long lifetime (>1012 cycles, no creep [5]) are demonstrated.

CMOS-integrated poly-SiGe cantilevers with read/write system for probe storage device

A poly-SiGe technology enabling a dense array of micro-cantilevers and tips on CMOS is demonstrated. Built from a dual-thickness structural layer, the cantilevers feature a very small initial bending and have a compliant torsional suspension with a stiffness of 3×10−10 Nm/rad. Sharp tips are formed in a low-temperature amorphous silicon layer by isotropic plasma etching. An electrical read/write system is formed by connecting the tip to the CMOS with a suspended platinum trace, running on top of the cantilever.

Cathodic Inhibition Effects during NiFe and ZnNi Alloy Deposition

Cathodic inhibition effects of nickel and iron ions on the proton reduction reaction are demonstrated in chloride, sulfate, and perchlorate solutions. They are not caused by metal hydrolysis but are induced electrochemically and linked to the anomalous codeposition of NiFe alloys. The addition of zinc ions to a nickel electrolyte also inhibits the reduction of protons and nickel ions. but this effect is not caused by an electrochemical reaction. Therefore it is suggested that the anomalous codeposition of ZnNi proceeds via a different mechanism than the anomalous electrodeposition of NiFe.

TSV metrology and inspection challenges

The interest in 3D packaging and specifically TSV processes has grown significantly in the past few years, with nearly every major chip manufacturer announcing plans to develop and implement this technology. As TSV process flows become stabilized, a number of metrology and inspection issues and opportunities have arisen. Many of these challenges are novel to the industry due to the relatively large size of the vias and new processes such as wafer back-grinding and carrier bonding. This paper summarizes the initial trial process monitoring that has been used during via-first TSV process development at IMEC. This process is designed for SiC (system in chip) applications, using Cu-filled vias measuring 5 um wide by 22 or 50 um deep. While there are a variety of metrology and inspection applications for TSV processing, the main topics covered here are via size measurement, post-grind wafer inspection, and carrier wafer bonding inspection.

Thermal curing of crystallographic defects on a slim-cut silicon foil

The SLIM-Cut method [1] addresses one of the most important challenges of crystalline-Si for photovoltaics: kerf-free wafering of substrates as thin as 50 microns. The SLIM-Cut technology is fully based on mechanical stress and it is compatible with low-cost fabrication methods: a stress field is applied to a silicon wafer so that a crack propagates in the silicon substrate parallel to the surface at a given depth. The top silicon layer is separated from the parent substrate and processed into a solar cell.