J. Van Aelst

3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias

Using standard single damascene type techniques on bulk-Si, combined on one hand with extreme wafer thinning and on the other with Cu-Cu thermo-compression bonding technology, the paper demonstrate yielding 10k through-wafer 3D-via chains with a via pitch of 10μm for a via diameter of 5μm. The bonded contacts exhibit shear strengths exceeding 40MPa. Measurements indicate there is no significant contact resistance at the Cu-Cu bonded interface: within measurement accuracy, the 4-point via chain resistance is consistent with bulk Cu resistivity

3D stacked IC demonstration using a through Silicon Via First approach

We report for the first time the demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of our reference 0.13 mum CMOS process on 200 mm wafers. The top die is thinned down to 25 mum and bonded to the landing wafer by Cu-Cu thermo-compression. Both top and landing wafers contain CMOS finished at M2 to evaluate the process impact both FEOL and BEOL. The results confirm no degradation of the FEOL performance. The functionality of various ring oscillator topologies that include inverters distributed over both top and bottom dies connected through TSVs demonstrates excellent chip integrity after the TSV and 3D stacking process.

Characterisation and integration feasibility of JSR's low-k dielectric LKD-5109

Increasing the circuit density is driving the need for lower permittivity interlayer dielectrics (ILD) to reduce the capacitance between long parallel lines. JSRs LKD-5109, an MSQ-based material, is one of such low-k materials for the 65-nm node. The feasibility of integrating LKD-5109 in a single inlaid structure has been investigated. Thermal stability, chemical compatibility to stripping agents and CMP slurries are verified. A single damascene structure incorporating a dual CVD hard mask has been attempted and electrical results have been evaluated.

Challenges of clean/strip processing for Cu/low-k technology

This presentation is an overview of clean/strip processing for low Cu/low-k technology. The paper starts with a brief analysis of dry etch processes that determine the issues in subsequent processes; in the case of porous low-k dielectrics, etch conditions must be carefully optimized to find an optimal balance between the polymer formation and plasma damage of low-k dielectrics. The presentation includes recent results related to dry and wet cleaning, plasma damage, and stability of low-k films. The wet cleaning of solutions using supercritical CO/sub 2/(SCCO/sub 2/)IPA/water mixtures and special surfactants will also be analyzed. Results obtained by different advanced techniques like FTIR, XPS, ellipsometric porosimetry (EP), energy filtered TEM (EFTEM), TOF SIMS etc have been used to characterize the residues, plasma damage and cleaning efficiency and they will be analyzed during the presentation.

Integration feasibility of porous SiLK* semiconductor dielectric

The feasibility of integrating a SiLK* Semiconductor Dielectric film (*trademark of The Dow Chemical Company) that contains closed pores was studied using a single damascene test vehicle. The study focussed on tool qualification, process set-up and single damascene feasibility to demonstrate technology extendibility. The results indicate that only minor changes have to be made to the process conditions when transitioning from a dense to a porous SiLK* film.

Role of dielectric and barrier integrity in reliability of sub-100 nm copper low-k interconnects

The purpose of this paper is to show the importance of both dielectric and diffusion barrier integrity in the TDDB (time dependent dielectric breakdown) reliability of sub-100 nm copper low-k interconnects. The impact of dielectric and barrier integrity on the model parameters is explained, providing easy guidance for correct interpretation of BEOL TDDB data.

Single damascene integration of porous Zirkon TM version 1 low- k dielectric films

ZirkonTM LK2000 version 1 dielectric film (ZirkonTM is a trademark of Shipley Company L.L.C), a porous methylsilsesquioxane (MSQ)-based spin-on dielectric with a k value targeted at 2.0, has been integrated in single damascene structures. For patterning, a dual SiC/SiO2 CVD hard-mask was used. Surface treatments (DUV ozone (DUV-O3), plasma treatments) were tested to solve the adhesion issues encountered at the CVD hard-mask and the low-k interface. Adhesion is only improved when plasma treatments are used. Analyses (FTIR, TDS, nano-indentation) show that the plasma treatments only modify the low-k surface. For integration, a plasma treatment (He, NH3, N2/O2) prior to deposition of the CVD hard-mask was included. After patterning, copper metallization and CMP of the wafers, electrical evaluation shows that, compared to the reference wafer (no plasma treatment), plasma-treated wafers have a higher yield and a lower sheet resistance. The RC delay is slightly higher for the plasma-treated wafers than for the reference wafer.

Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274/spl mu/m/sup 2/ 6T-SRAM cell and advanced CMOS logic circuits

We present the fabrication process of a fully functional 0.274/spl mu/m2 6T-SRAM cell with inserted-Ta/sub x/N/sub y/ tall tripple gate devices. Several advancements over our previous report by A. Naekaerts et al. (2004) are: reduction of the 6T-SRAM cell size from 0.314 to 0.274/spl mu/m2 using further litho process optimizations; insertion of 5nm TaN-based layer in the gate stack of the cell devices; improved OPC for CD control and integration of SRAM and logic. A high static noise margin of 216mV at 1.0V has been achieved with devices having a Lg=37nm. This is the smallest 6T-SRAM cell with MG devices reported so far.

Integration of Single Damascene 85/85 nm L/S copper trenches in Black Diamond using 193 nm optical lithography with dipole illumination

This paper describes the integration of Single Damascene 85/85 nm L/S copper trenches in Black Diamond (Applied Materials) dielectric (k=2.85). Optical lithography (193 nm) with off-axis illumination was used to print the trenches. Integration issues are discussed, and resistance and RC delay data are presented. The method is applied to study the resistivity for sub 100 nm copper lines.

Towards biolubricant compatible vegetable oils by pore mouth hydrogenation with shape-selective Pt/ZSM-5 catalysts

Pt/ZSM-5 catalysts with various crystal sizes were prepared via competitive ion-exchange, followed by a slow activation procedure. Even when using very large ZSM-5 crystals, highly dispersed Pt nano-clusters were contained within the zeolite crystals voids, as ascertained by 2D pressure-jump IR spectroscopy of adsorbed CO and focussed ion-beam transmission electron microscopy. The shape-selective properties of the Pt/ZSM-5 catalysts were evaluated in the partial hydrogenation of soybean oil. Unique hydrogenation selectivities were observed, as the fatty acids located at the central position of the triacylglycerol (TAG) molecules were preferentially hydrogenated. The resulting oil has therefore high levels of intermediately melting TAGs, which are compatible with biolubricants due to their improved oxidative stability and still appropriate low-temperature fluidity. The TAG distribution in the partially hydrogenated soybean oil samples was independent from the zeolite crystal size, while the hydrogenation activity linearly increases with the crystals external surface area. This trend was confirmed with a Pt loaded mesoporous ZSM-5 zeolite, obtained via a mild alkaline treatment. These observations imply and confirm a genuine pore mouth catalysis mechanism, in which only one fatty acid chain of the TAG is able to enter the micropores of ZSM-5, where the double bonds are hydrogenated by the crystal encapsulated Pt-clusters.