Robin Roelofs

Time dependent dielectric breakdown (TDDB) evaluation of PE-ALD SiN gate dielectrics on AlGaN/GaN recessed gate D-mode MIS-HEMTs and E-mode MIS-FETs

This paper reports a comprehensive time dependent dielectric breakdown (TDDB) evaluation of recessed-gate devices with five different AlGaN barrier thicknesses with characteristics ranging from a D-mode MIS-HEMT to an E-mode MIS-FET. First, the fitted parameter β (the slope of the Weibull distribution) was smaller for a deeper recessed gate and larger for a thicker gate dielectric. Secondly, the extrapolated VG (criterium of 0.01% failures after 20 years) for the devices with Wg (gate width) = 10μm was lower when less AlGaN barrier remains under the gate. However, the extrapolated VG was increased when the AlGaN barrier was completely removed. Thirdly, a deeper recessed gate could result in a dominant percolation path due to a thinner gate dielectric on the sidewall of the gate recess edge. Fourthly, the Weibull distribution could scale with the gate width, indicating an intrinsic failure. Finally, the lifetime was extrapolated to 0.01% of failures for Wg=36mm at 150oC after 20 years by fitting the data with a power law or an exponential law to gate voltages of 4.9V and 7.2V, respectively.

Correlation of interface states/border traps and threshold voltage shift on AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors

In this paper, three electrical techniques (frequency dependent conductance analysis, AC transconductance (AC-gm), and positive gate bias stress) were used to evaluate three different gate dielectrics (Plasma-Enhanced Atomic Layer Deposition Si3N4, Rapid Thermal Chemical Vapor Deposition Si3N4, and Atomic Layer Deposition (ALD) Al2O3) for AlGaN/GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistors. From these measurements, the interface state density (Dit), the amount of border traps, and the threshold voltage (VTH) shift during a positive gate bias stress can be obtained. The results show that the VTH shift during a positive gate bias stress is highly correlated to not only interface states but also border traps in the dielectric. A physical model is proposed describing that electrons can be trapped by both interface states and border traps. Therefore, in order to minimize the VTH shift during a positive gate bias stress, the gate dielectric needs to have a lower interface state density an...

Material insights of HfO2-based integrated 1-transistor-1-resistor resistive random access memory devices processed by batch atomic layer deposition.

With the continuous scaling of resistive random access memory (RRAM) devices, in-depth understanding of the physical mechanism and the material issues, particularly by directly studying integrated cells, become more and more important to further improve the device performances. In this work, HfO2-based integrated 1-transistor-1-resistor (1T1R) RRAM devices were processed in a standard 0.25 μm complementary-metal-oxide-semiconductor (CMOS) process line, using a batch atomic layer deposition (ALD) tool, which is particularly designed for mass production. We demonstrate a systematic study on TiN/Ti/HfO2/TiN/Si RRAM devices to correlate key material factors (nano-crystallites and carbon impurities) with the filament type resistive switching (RS) behaviours. The augmentation of the nano-crystallites density in the film increases the forming voltage of devices and its variation. Carbon residues in HfO2 films turn out to be an even more significant factor strongly impacting the RS behaviour. A relatively higher deposition temperature of 300 °C dramatically reduces the residual carbon concentration, thus leading to enhanced RS performances of devices, including lower power consumption, better endurance and higher reliability. Such thorough understanding on physical mechanism of RS and the correlation between material and device performances will facilitate the realization of high density and reliable embedded RRAM devices with low power consumption.

The impact of the gate dielectric quality in developing Au-free D-mode and E-mode recessed gate AlGaN/GaN transistors on a 200mm Si substrate

The selection of the gate dielectric is one of the most critical stability issues in recessed gate AlGaN/GaN transistors. In this work, we show that the quality of the gate dielectric has a strong impact on: 1) the threshold voltage (VTH) hysteresis, 2) the drain current reduction for enhancement mode devices, and 3) the forward gate bias TDDB (time dependent dielectric breakdown). It will be shown that the VTH hysteresis and the current reduction can be minimized by using a dielectric with lower interface state density (Dit) and less border traps, e.g., a PE-ALD SiN dielectric. Furthermore, the 0.01% failures at 20 years TDDB requirement at 150°C for a large power device, e.g., gate width Wg=36mm, necessitates the use of at least a 25nm-thick PE-ALD SiN gate dielectric.

Combined plasma-enhanced-atomic-layer-deposition gate dielectric and in situ SiN cap layer for reduced threshold voltage shift and dynamic ON-resistance dispersion of AlGaN/GaN high electron mobility transistors on 200 mm Si substrates

In this work we will present the experimental path followed to optimize the dynamic ON-resistance (RDS-ON) dispersion and to reduce the threshold voltage shift of AlGaN/GaN transistors grown on 200 mm Si wafers. Firstly, it will be demonstrated that a SiN gate dielectric grown by means of plasma enhanced atomic layer deposition (PEALD) instead of rapid thermal chemical vapor deposition (RTCVD) reduces threshold voltage (Vth) shift induced by negative gate bias and the gate leakage. Secondly, the dynamic RDS-ON dispersion of two wafers with same gate dielectric (PEALD SiN) but different in situ metal organic chemical vapor deposition (MOCVD) capping layer, GaN or SiN, is compared. Results will show that the traps at the surface causing the RDS-ON dispersion can drastically be reduced by using in situ MOCVD SiN.

Impact of temperature on conduction mechanisms and switching parameters in HfO2-based 1T-1R resistive random access memories devices

In this work, the impact of temperature in the range from −40 to +150 °C on the leakage mechanism and resistive switching voltages of 1T-1R HfO2-based devices is investigated. By using incremental step pulses with an additional read and verify algorithm, the devices are switched from the high resistive state (HRS) to the low resistive state (LRS) and vice versa. In the HRS, the leakage current values are not affected by the temperature, suggesting a tunnel-like conduction mechanism through the filament constriction. By applying the quantum-point contact model, this temperature independence is attributed to compensation between the width and the height variations of the tunnel barrier. In contrast to the HRS, the leakage currents values of the LRS are decreasing linearly with raising temperature, suggesting a metal-like conduction mechanism. Therefore, the on/off ratio is slightly decreasing with increasing temperature. Regarding the switching voltages, no impact of temperature was found, ensuring stable s...

Reduction of the Cell-to-Cell Variability in Hf1-xAlxOy Based RRAM Arrays by Using Program Algorithms

In this letter, we propose an effective route to reduce the cell-to-cell variability in 1T-1R-based random access memories (RRAM) arrays by combining the excellent switching performance of Hf1-xAlxOy with an optimized incremental step pulse with verify algorithm for programming. The strongly reduced cell-to-cell variability improves the thermal and post-programming stability of the arrays, which is relevant for many applications of the RRAM technology. Finally, the retention study at 150 °C enables the prediction of the data storage capability.

Impact of the precursor chemistry and process conditions on the cell-to-cell variability in 1T-1R based HfO 2 RRAM devices

The Resistive RAM (RRAM) technology is currently in a level of maturity that calls for its integration into CMOS compatible memory arrays. This CMOS integration requires a perfect understanding of the cells performance and reliability in relation to the deposition processes used for their manufacturing. In this paper, the impact of the precursor chemistries and process conditions on the performance of HfO2 based memristive cells is studied. An extensive characterization of HfO2 based 1T1R cells, a comparison of the cell-to-cell variability, and reliability study is performed. The cells’ behaviors during forming, set, and reset operations are monitored in order to relate their features to conductive filament properties and process-induced variability of the switching parameters. The modeling of the high resistance state (HRS) is performed by applying the Quantum-Point Contact model to assess the link between the deposition condition and the precursor chemistry with the resulting physical cells characteristics.