Michael Givens

Temperature dependence of frequency dispersion in III–V metal-oxide-semiconductor C-V and the capture/emission process of border traps

This paper presents a detailed investigation of the temperature dependence of frequency dispersion observed in capacitance-voltage (C-V) measurements of III-V metal-oxide-semiconductor (MOS) devices. The dispersion in the accumulation region of the capacitance data is found to change from 4%–9% (per decade frequency) to ∼0% when the temperature is reduced from 300 K to 4 K in a wide range of MOS capacitors with different gate dielectrics and III-V substrates. We show that such significant temperature dependence of C-V frequency dispersion cannot be due to the temperature dependence of channel electrostatics, i.e., carrier density and surface potential. We also show that the temperature dependence of frequency dispersion, and hence, the capture/emission process of border traps can be modeled by a combination of tunneling and a “temperature-activated” process described by a non-radiative multi-phonon model, instead of a widely believed single-step elastic tunneling process.

Ozone Based Atomic Layer Deposition of Hafnium Oxide and Impact of Nitrogen Oxide Species

It has recently been reported that nitrogen oxide species (e.g., N 2 O 5 , NO 2 , NO 3 , and/or N 2 O) can have an impact on ozone based atomic layer deposition (ALD) of metal oxides when ozone is generated by dielectric barrier discharge (DBD) in O 2 /N 2 mixtures. In this work, we further investigate the effect of the O 2 /N 2 ratio in the DBD for Hfo 2 ALD using HfCl 4 as metal precursor. Using O 3 in the absence of nitrogen oxides, uniform HfO 2 layers are obtained between 200 and 250°C in a hot wall cross flow reactor. The self-limiting nature of the O 3 and HfCl 4 reaction is demonstrated at 225°C and the growth-per-cycle is 0.12 nm. At higher temperature, O 3 decomposes at the HfO 2 coated reactor walls, resulting in a decreasing HfO 2 thickness over Si substrates in the direction of the gas flow. Using O 3 in combination with nitrogen oxides by DBD in N 2 /O 2 mixtures, we obtained uniform HfO 2 layers in the 200-300°C temperature range. At 300°C, the GPC is 0.14 nm and the HfO 2 films show a low impurity content. Both processes produce high quality dielectric layers in Pt gated capacitors.

Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

We report record results for III-V gate-all-around devices fabricated on 300mm Si wafers. A gm of 2200 μS/μm with an SSsat of 110 mV/dec is achieved for an Lg=50nm device using a newly developed gate stack interlayer material deposited by ALD. In addition it is shown that high pressure annealing can further improve device performance with an average increase in gm of 22% for a 400 °C anneal.

New Mechanisms for Ozone-Based ALD Growth of High-k Dielectrics via Nitrogen-Oxygen Species

Ozone (O3) is a commonly used oxidant in ALD of various high-k metal oxides. Commercially available ozone delivery systems commonly rely on the dielectric barrier discharge and often utilize nitrogen in the feed gas to provide consistent ozone generation. Through a complex series of plasma reactions, various NxOy species can also form within the corona from O2 in the presence of N2. These species, while present in various concentrations in the generator effluent, are unregulated by the delivery system which measures and actively controls the O3 concentration only.

Si-passivated Ge nMOS gate stack with low Dit and dipole-induced superior PBTI reliability using 3D-compatible ALD caps and high-pressure anneal

We demonstrate a Si-passivated Ge nMOS gate stack with Dit of ∼5×10¹⁰ cm⁻²eV⁻¹ around midgap and unnoticeable C-V hysteresis at an operating condition (oxide trap density of ∼1×10⁸ cm⁻² at V<inf>ov</inf>/CET=3.5 MV/cm). Insertion of a 3D-compatible thin ALD LaOx, MgOx and LaSiO layer at the interface between HfO2 and SiO2/Si/Ge improves PBTI reliability thanks to the interface dipole-induced band engineering. The high DIT of Si-passivated Ge nFET is dramatically reduced by ∼40x around midgap using a combination of the LaSiO insertion and a H2 high-pressure anneal (HPA). These key gate stack technologies realize further improvements in mobility (∼50% at peak) and PBTI reliability (V<inf>ov</inf>=0.32 V for 10 years) of Si-passivated Ge nFETs.

Gate stack thermal stability and PBTI reliability challenges for 3D sequential integration: Demonstration of a suitable gate stack for top and bottom tier nMOS

3D Sequential integration has been envisioned to stack transistors in the same front-end process. A crucial challenge is the management of the thermal budget. This work focuses on Si nMOS gate stack challenges, specifically: for a top tier device, by inserting a thin LaSiOx interlayer between SiO2 and HfO2 a sufficient PBTI reliability is demonstrated without resorting to unsuitable high temperature anneals. This gate stack also offers good thermal stability for a pMOS over nMOS scenario.

Nickel suicide for source-drain contacts from ALD NiO films

In this work, we demonstrate the preparation of nickel monosilicide (NiSi) layers on silicon using a conformal NiO ALD process and thin sacrificial Ge interlayers. The interlayers protect the underlying Si from oxidizing during the NiO growth, while allowing for Ni diffusion during a silicidation anneal. The NiSi layers prepared have low amounts of impurities and near bulk resistivities, therefore making the processes promising candidates for applications in advanced semiconductor devices where high quality NiSi layers are needed, such as source-drain contacts. Good step coverage provided by ALD enables their use for example in non-planar transistors such as FinFETs and other multi-gate transistors with complex topographies.

BTI reliability of InGaAs nMOS gate-stack: On the impact of shallow and deep defect bands on the operating voltage range of III-V technology

In this work, we show that the reliability of InGaAs channel MOS devices not only depends on density of shallow defect states (i.e., electron traps responsible for PBTI in Si devices), but it is also governed by the density of deep defect states. This limits the operating range of the device. We conclude that it is necessary to characterize both shallow and deep defect densities in order to determine the total operating window (i.e., maximum underdrive and overdrive) of III-V devices for future technologies. We also show that a gate-stack comprising of a new ASM interface layer (ASM-IL), a LaSiOx interlayer and high-k dielectric can achieve the required reliability targets for a low power technology such as III-V.

Impact of the precursor chemistry and process conditions on the cell-to-cell variability in 1T-1R based HfO 2 RRAM devices

The Resistive RAM (RRAM) technology is currently in a level of maturity that calls for its integration into CMOS compatible memory arrays. This CMOS integration requires a perfect understanding of the cells performance and reliability in relation to the deposition processes used for their manufacturing. In this paper, the impact of the precursor chemistries and process conditions on the performance of HfO2 based memristive cells is studied. An extensive characterization of HfO2 based 1T1R cells, a comparison of the cell-to-cell variability, and reliability study is performed. The cells’ behaviors during forming, set, and reset operations are monitored in order to relate their features to conductive filament properties and process-induced variability of the switching parameters. The modeling of the high resistance state (HRS) is performed by applying the Quantum-Point Contact model to assess the link between the deposition condition and the precursor chemistry with the resulting physical cells characteristics.

First demonstration of ∼3500 cm 2 /V-s electron mobility and sufficient BTI reliability (max V ov up to 0.6V) In 0.53 Ga 0.47 As nFET using an IL/LaSiO x /HfO 2 gate stack

In this paper, we demonstrate for the first time an implant free In<inf>0.53</inf>Ga<inf>0.47</inf>As n-MOSFET that meets the reliability target for advanced technology nodes with a max operating V<inf>ov</inf> of 0.6 V. In addition, an excellent electron mobility (μ<inf>eff, peak</inf>=3531 cm2/V-s), low SS<inf>lin</inf>=71 mV/dec and an EOT of 1.15 nm were obtained. We also report the scaling potential of this stack to 1nm EOT without loss of performance, reliability and further reduction of the sub-threshold swing (SS<inf>lin</inf>=68mV/dec). On top of the novel IL we presented last year, in this paper we insert a LaSiO<inf>x</inf> layer between the IL and HfO<inf>2</inf> offering an increased chemical stability of the gate stack. This combination is key and offers both an improved interface quality as well as a reduction of the oxide trap density.