Jarrod Eliason

A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process

A low-voltage (1.3 V) 64-Mb ferroelectric random access memory (FRAM) using a one-transistor one-capacitor (1T1C) cell has been fabricated using a state-of-the-art 130-nm transistor and a five-level Cu/flouro-silicate glass (FSG) interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate-oxide low-voltage logic process. Novel overwrite sense amplifier and programmable ferroelectric reference generation schemes are employed for fast reliable read-write cycle operation. Address access time for the memory is less than 30 ns while consuming less than 0.8 mW/MHz at 1.37 V. An embedded FRAM (eFRAM) density of 1.13 Mb/mm/sup 2/ is achieved with a cell size of 0.54 /spl mu/m/sup 2/ and capacitor size of 0.25 /spl mu/m/sup 2/.

Manufacturable High-Density 8 Mbit One Transistor?One Capacitor Embedded Ferroelectric Random Access Memory

Enhanced yield and reliability through process improvements, leading to a manufacturable process for a full-bit functional 8 Mbit one transitor–one capacitor (1T–1C) embedded ferroelectric random access memory (eFRAM) fabricated within a low-leakage 130 nm, 5 lm Cu/fluorosilicate glass (FSG) interconnect complementary metal oxide semiconductor (CMOS) logic process, are described. Higher signal margins are further enabled by the single-bit substitution methodology that replaces bits at the low-end of the original distribution with redundant elements. Retention tests on wafers with signal margins above a threshold value for screen show no bit fails for bakes extending up to 1000 h, suggesting retention lifetimes of more than 10 years at 85 °C. Using the qualified process reported in this paper, commercial products are being routinely produced in our fabrication facilities.

Reliability of Ferroelectric Random Access memory embedded within 130nm CMOS

We present results of a comprehensive reliability evaluation of a 2T–2C, 4Mb, Ferroelectric Random Access Memory embedded within a standard 130nm, 5LM Cu CMOS platform. Wear-out free endurance to 5.4×1013 cycles and data retention equivalent of 10 years at 85°C is demonstrated. The results show that the technology can be used in a wide range of applications including embedded processing.

Full-Bit Functional, High-Density 8 Mbit One Transistor–One Capacitor Ferroelectric Random Access Memory Embedded within a Low-Power 130 nm Logic Process

We report the electrical properties of a full-bit functional 8 Mbit one transitor–one capacitor (1T–1C) embedded ferroelectric random access memory (eFRAM) fabricated within a low-leakage 130 nm 5 lm Cu interconnect complementary metal oxide semiconductor (CMOS) logic process. To increase manufacturability and reliability margins, we have introduced a single-bit substitution methodology that replaces bits at the low-end of the original distribution with redundant elements leading to an increased signal margin. Further, we have fabricated a digital signal processor (DSP) using the eFRAM process flow and have shown that the operating frequency is nearly the same relative to the CMOS baseline. With the development of logic-compatible eFRAM, we have created a technology platform that enables ultra-low-power devices.

An 8Mb 1T1C ferroelectric memory with zero cancellation and micro-granularity redundancy

New design techniques facilitate a high reliability 1T1C 8Mb ferroelectric random access memory with 0.71u2 cell operating at 1.5V on a 130nm 5LM Cu process. Zero cancellation increases the cell interrogation voltage by using a nonswitching ferroelectric capacitor to remove charge from the bit line that compensates the linear charge from the cell capacitor. A micro-granularity redundancy approach preserves high repair probability for up to 128 single bit failures. Trim data is stored in 2T2C configuration rows for redundancy, reference, regulator and control logic adjustment

Reliability Demonstration of a Ferroelectric Random Access Memory Embedded within a 130nm CMOS Process

Reliable operation of a 4 Mb ferroelectric random access memory (FRAM) embedded within a standard 130 nm CMOS process is demonstrated. Intrinsic endurance test to 5.4×1012 cycles shows no degradation of switched polarization. 10 year, 85degC, data retention life is demonstrated with 125°C data bake to 1,000 Hrs with no fails.

Reliability characterization of a Ferroelectric Random Access Memory embedded within 130nm CMOS

Reliability data is presented for a 4Mb Ferroelectric Random Access Memory (F-RAM) embedded within a 130nm CMOS process. Write/read endurance in the device exhibits stable intrinsic bit properties through 2.7x1013 cycles. Data retention demonstrates 10 year, 85°C operating life. No fails were observed with full-chip endurance test to 108 cycles followed by 1,000 hours of data retention bake at 125°C. Robust process reliability is demonstrated with no fails at 125°C operating life test.

High-Density 8Mb 1T-1C Ferroelectric Random Access Memory Embedded Within a Low-Power 130nm Logic Process

Ferroelectric memories are the most promising alternative to traditional embedded nonvolatile memories, such as flash and EEPROMs, because of their fast read/write cycle time, non-volatile data retention, low voltage/low power operation and low number of additional masks for fabrication (+2). An embedded ferroelectric memory (FRAM) has been developed using a 1.5 V, 130 nm 5 metal layer Cu/FSG logic process. The only modification to the logic process was the addition of a ferroelectric process module consisting of two additional masks (FECAP, VIAO) immediately before MET1. The ferroelectric was 70 nm Pb(Zr,Ti)O3 (PZT) deposited by metalorganic chemical vapor deposition (MOCVD). The electrical properties of a 8 Mb 1T-1C embedded FRAM were characterized. This eFRAM process has been used to simultaneously fabricate a digital signal processor (DSP) using the eFRAM process flow and the operating frequency is nearly the same relative to the CMOS baseline. This eFRAM process flow creates a technology platform that enables ultra-low-power devices.

Ferroelectric nonvolatile logic

Abstract This paper describes the design of nonvolatile logic elements using ferroelectric materials. Two separate approaches are discussed. The first approach involves shadowing a CMOS latch or flip-flop with a single bit 2T/2C ferroelectric memory. The second approach offers improved density by integrating ferroelectric capacitors within the logic element. Both designs employ non-switching ferroelectric capacitors to establish the optimum bit line load in the absence of sufficient parasitic capacitance. The paper further describes low-voltage and wide-voltage design techniques used to realize 2.7 – 5.5V products on a “5-volt” ferroelectric process. These same techniques allow 1.8V ferroelectric memory products to be designed using the upcoming generation of production ready “3-volt” ferroelectric materials. Layout effects are discussed, as well as bit/cell ratio optimization.

Composite bitmap visualization techniques for advanced ferroelectric memories

The year 2007 was a breakout year for advanced F-RAM. Two products manufactured on Texas Instruments¿ 130nm ferroelectric memory process are now commercially available from Ramtron, and TI announced its intention to leverage the benefits of F-RAM in next generation RFID products. New composite bitmap visualization software created by Ramtron aided the development of a reliable process and manufacturable products. This paper will describe and demonstrate some of the powerful data analysis techniques enabled by this software.