K. Remack

A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process

A low-voltage (1.3 V) 64-Mb ferroelectric random access memory (FRAM) using a one-transistor one-capacitor (1T1C) cell has been fabricated using a state-of-the-art 130-nm transistor and a five-level Cu/flouro-silicate glass (FSG) interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate-oxide low-voltage logic process. Novel overwrite sense amplifier and programmable ferroelectric reference generation schemes are employed for fast reliable read-write cycle operation. Address access time for the memory is less than 30 ns while consuming less than 0.8 mW/MHz at 1.37 V. An embedded FRAM (eFRAM) density of 1.13 Mb/mm/sup 2/ is achieved with a cell size of 0.54 /spl mu/m/sup 2/ and capacitor size of 0.25 /spl mu/m/sup 2/.

Reliability properties of low-voltage ferroelectric capacitors and memory arrays

We report on the reliability properties of ferroelectric capacitors and memory arrays embedded in a 130-nm CMOS logic process with 5LM Cu/FSG. Low voltage (<1.5 V) operation is enabled by the 70-nm thick MOCVD PZT ferroelectric films. Data loss resulting from high temperature bakes is primarily caused by the imprint effect, which shows /spl sim/1.5 eV time-to-fail activation energy. Excellent bit endurance properties are observed on fully packaged memory arrays, with no degradation up to 10/sup 13/ write/read polarization switching cycles. Retention measured after 10/sup 12/ switching cycles demonstrates no degradation relative to arrays with minimal cycling.

Reliability of Ferroelectric Random Access memory embedded within 130nm CMOS

We present results of a comprehensive reliability evaluation of a 2T–2C, 4Mb, Ferroelectric Random Access Memory embedded within a standard 130nm, 5LM Cu CMOS platform. Wear-out free endurance to 5.4×1013 cycles and data retention equivalent of 10 years at 85°C is demonstrated. The results show that the technology can be used in a wide range of applications including embedded processing.

Embedded ferroelectric memory using a 130-nm 5 metal layer Cu / FSG logic process

An embedded ferroelectric memory (FRAM) has been developed using a 1.5V, 130nm 5 metal layer Cu / FSG logic process. The only modification to the logic process was the addition of a ferroelectric process consisting of two additional masks (FECAP, VIA0) immediately before MET1. The ferroelectric was 70nm Pb(Zr,Ti)O3 (PZT) deposited by metalorganic chemical vapor deposition (MOCVD). The bit distribution of small ferroelectric capacitors (< 0.2 /spl mu/m/sup 2/) was measured after fabrication and bake. A reasonable amount of property degradation after 6000hr 125/spl deg/C bake was observed.

Reliability Demonstration of a Ferroelectric Random Access Memory Embedded within a 130nm CMOS Process

Reliable operation of a 4 Mb ferroelectric random access memory (FRAM) embedded within a standard 130 nm CMOS process is demonstrated. Intrinsic endurance test to 5.4×1012 cycles shows no degradation of switched polarization. 10 year, 85degC, data retention life is demonstrated with 125°C data bake to 1,000 Hrs with no fails.

Reliability characterization of a Ferroelectric Random Access Memory embedded within 130nm CMOS

Reliability data is presented for a 4Mb Ferroelectric Random Access Memory (F-RAM) embedded within a 130nm CMOS process. Write/read endurance in the device exhibits stable intrinsic bit properties through 2.7x1013 cycles. Data retention demonstrates 10 year, 85°C operating life. No fails were observed with full-chip endurance test to 108 cycles followed by 1,000 hours of data retention bake at 125°C. Robust process reliability is demonstrated with no fails at 125°C operating life test.

High-Density 8Mb 1T-1C Ferroelectric Random Access Memory Embedded Within a Low-Power 130nm Logic Process

Ferroelectric memories are the most promising alternative to traditional embedded nonvolatile memories, such as flash and EEPROMs, because of their fast read/write cycle time, non-volatile data retention, low voltage/low power operation and low number of additional masks for fabrication (+2). An embedded ferroelectric memory (FRAM) has been developed using a 1.5 V, 130 nm 5 metal layer Cu/FSG logic process. The only modification to the logic process was the addition of a ferroelectric process module consisting of two additional masks (FECAP, VIAO) immediately before MET1. The ferroelectric was 70 nm Pb(Zr,Ti)O3 (PZT) deposited by metalorganic chemical vapor deposition (MOCVD). The electrical properties of a 8 Mb 1T-1C embedded FRAM were characterized. This eFRAM process has been used to simultaneously fabricate a digital signal processor (DSP) using the eFRAM process flow and the operating frequency is nearly the same relative to the CMOS baseline. This eFRAM process flow creates a technology platform that enables ultra-low-power devices.

Integration and bit distribution of production-worthy FRAM embedded with 130nm CMOS logic

High density embedded FRAM has been fabricated within a 130nm, 5LM Cu/FSG CMOS logic process with only two additional masks. Integrated arrays, fabricated with 70nm-thick MOCVD lead zirconate titanate (PZT) as the ferroelectric and Ir/IrO2 electrodes, show good separation voltage and wide signal margin between the two data states. Ferroelectric processing does not adversely affect the CMOS properties. Opposite state retention measurements of the arrays project greater than 10 years lifetime at 85degC