Jatmiko E. Suseno

Body doping influence in vertical MOSFET design

The vertical MOSFET is considered as an alternative to nanoscale device structure, due to relaxed-dependence on lithography and easier double gate realization. In this paper, the influence of body doping concentration variation in vertical MOSFET developed using oblique-rotating implantation (ORI) method is investigated. For this purpose, two-dimensional process simulation was made using TCAD tools for several Nsub, namely 1, 4, 7 ad 10.1018 cm−3, respectively. The electrical characteristic and short channel effect i.e. DIBL and subthreshold swing, for different body doping were deliberated. The result also suggests the required change in the pillar design in maintaining the gate channel.

Physics-Based Simulation of Carrier Velocity in 2-Dimensional P-Type MOSFET

The carrier velocity for 2-dimensional (2-D) p-type nanostructure was simulated in this paper. According to the energy band diagram, the effective mass (m*) in the p-type silicon is mostly dominated by heavy hole because of the large gap between heavy hole and light hole in k = 0. The carrier concentration calculation for 2-D, based on the Fermi – Dirac statistic on the order of zero ( ), was applied to obtain the intrinsic velocity of carrier, in the term of thermal velocity vth. The results for 2-D carrier velocity were modeled and simulated, and the comparison for degenerate and non-degenerate regime is presented for various temperature and concentration. It is revealed that the velocity is strongly dependent on concentration and becomes independent of temperature at high concentration.

Short channel effect of SOI vertical sidewall MOSFET

Application of asymmetric sidewall vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple process simulation has been developed to reduce the parasitic overlap capacitance in the asymmetric sidewalls vertical MOSFETs by using SOI (silicon on insulator) in bottom planar surfaces side. The result shows that while channel length decreases, the threshold voltage goes lower, the DIBL rises and subthreshold swing tends to decrease, for both structures. It is noted that the SVS MOSFET structure generally have better performance in SCE control compared to bulk vertical MOSFET. The presence of buried oxide is believed to increase the performance of vertical MOSFET, essentially in controlling the depletion in subthreshold voltage.

Extraction of SPICE Model for Double Gate Vertical MOSFET

Vertical MOSFETs device have one important disadvantage, which is higher overlap capacitances such as the separated gate-source and gate-drain parasitic capacitances (CGSO and CGDO), which is known to be most crucial to the high-frequency/speed performance but very hard to extract. In this paper presents parameter extraction techniques to create an extended BSIMxa0xa0model card of vertical p-MOSFETs for circuit simulation with SPICE can be accurately obtained for these overlap capacitances determination.This device was modeled as a subcircuit with any sub elements such as resistors, capacitors and diodes that capture the parasitic effects. The subcircuit was simplified in order to modeling in BSIM easily. The overlap capacitances of vertical p-MOSFET can be determined by using capacitance parameter extraction of quasi static small signal equivalent circuit. The result showed that gate-drain paracitic capacitance (CGDO) is larger thanxa0xa0gate-source parasitic capacitance (CGSO).

Artificial intelligence techniques for SPICE optimization of MOSFET modeling

This paper proposes new method for optimize and verified electric characterization graph of MOSFET by using artificial neural network. Optimization using Neural Network (ONN) will compare current-voltage (I–V) Characteristic graph between the TCAD simulation and TSPICE modeling as desire data control a model parameter of BSIM. In this paper, the neural network method is dynamic feedforward Neural Network. After NN training, the best result is at Neural Network architecture of 36-30-10-5 with Mean Squared Error (MSE) of 1e-28 at epoch of 5.

An Analytical Threshold Voltage Model for the Vertical Sidewall Mosfet with a Curved-Channel

We present a new analytical model for surface potential and threshold voltage (Vth) for Single Gate Vertical MOSFET with curved channel. The influence of the corner effect in single gate vertical MOSFET is studied using two dimensional Poisson equation in both planar and spherical geometries. The electric field of the channel in single gate vertical MOSFET and impact on the threshold are studied. The relationship between the threshold voltage (Vth), channel length (L), channel concentration (NA), and the curved corner radius (r0) is given. The comparison with planar devices is provided. The characterization of single gate MOSFETs with curved-channel devices is attributed to the corner effect of the surface potential along the channel. The relationship between the minimum surface potential and the structure parameters is theoretically analyzed. Results confirm that the curved-channel of device gives contribution of the threshold voltage value and the Short Channel Effect (SCE)reduction of the device due to effects of the corner and gate oxide capacitance. These results show a good agreement with the numerical 2-D TCAD simulations. n nKeywords: Vertical MOSFET, Curved Channel, Analytical Model, Threshold Voltage, Short Channel Effect (SCE), Potential Barrier.

Investigation of short channel immunity of fully depleted double gate MOS with vertical structure

The electrical performance of fully depleted double gate MOSFET devices with vertical structure feature were evaluated with the implementation of oblique rotating implantation (ORI) method for several silicon pillar thicknesses using virtual wafer tool. The difference in the subthreshold performance is well noticed, as well as the potentials across the channel for different geometries. The implication of channel length reduction shows that in fully depleted feature, thinner pillar will result in better subthreshold performances than the thicker structure while maintaining the high on-current. As a result, thinner pillar delivers better short channel characteristic control in further channel scaling up to 20 nm.