Munawar A. Riyadi

Concentration dependence of drift and magnetoresistance ballistic mobility in a scaled-down metal-oxide semiconductor field-effect transistor

The degradation of ballistic mobility in a metal-oxide semiconductor field-effect transistor is attributed to the nonstationary ballistic injection from the contacts as the length of a channel shrinks to the length smaller than the scattering-limited mean free path. Apparent contradiction between the rise of magnetoresistance mobility and fall of drift mobility with increasing channel concentration is attributed to scattering-dependent magnetoresistance factor. The ballistic mean free path of injected carriers is found to be substantially higher than the long-channel drift mean free path. Excellent agreement with the experimental data on length-limited ballistic mobility is obtained.

Ballistic mobility degradation in scaled-down channel of a MOSFET

The ballistic mobility data by Luskawoski et. al [1] is interpreted by using recently published formalism [2]. The mobility is shown to be ballistic when the ballistic mean free path in a nanoscale transistor exceeds the channel length. This ballistic mobility affects the critical voltage Vc that can be as low as the thermal voltage 2 Vt (0.0518 V at room temperature) for a quasi-2-domensional (Q2D) nanostructure at the onset of nonlinearity in current-voltage relationship. The applied voltage V=0.08 V is higher than the thermal voltage triggering decline of mobility at low channel lengths due to high fields present. The general formalism is in excellent agreement with the experimental data.

Design and simulation analysis of nanoscale vertical MOSFET technology

Design consideration of vertical MOSFET with double gate structure on each side of insulating pillar for nanodevice applications is presented. The body doping effect on vertical channel for channel length, Lg = 50nm and analyzing its effect towards such small devices was successfully performed. The analysis continued with the comparative investigation of device performance with conventional planar MOSFET as scaling Lg down to 50nm. The final part evaluates the innovative design of incorporating dielectric pocket (DP) on top of vertical MOSFET turret with comprehensive device performance analysis as compared to standard vertical MOSFET in nanoscale realm. An optimized body doping for enhanced performance of vertical MOSFET was revealed. The vicinity of DP near the drain end is found to reduce the charge sharing effects between source and drain that gives better gate control of the depletion region for short channel effect (SCE) suppression in nanodevice structure.

Numerical study of fermi energy for p-type silicon nanowire

There is huge interest in the development of one dimensional silicon nanowire with extremely narrow cylindrical channel body as these devices are promising to take CMOS to the end‐of‐the‐roadmap. The band structure of Silicon is parabolic, in this condition density of state proportion of Fermi‐Dirac integral that covers the carrier statistics to all degeneracy level is presented and its limits are obtained. In the nondegenerate regime the results replicate what is expected form, the Boltzmann statistics. However, the results vary in degenerate regime. Fermi energy with respect to band edge is function of temperature that independent of the carrier concentration in the nondegenrate regime. In the other strongly degenerate, the Fermi energy is a function of carrier concentration appropriate for given dimensionality, but is independent of temperature.

Body doping influence in vertical MOSFET design

The vertical MOSFET is considered as an alternative to nanoscale device structure, due to relaxed-dependence on lithography and easier double gate realization. In this paper, the influence of body doping concentration variation in vertical MOSFET developed using oblique-rotating implantation (ORI) method is investigated. For this purpose, two-dimensional process simulation was made using TCAD tools for several Nsub, namely 1, 4, 7 ad 10.1018 cm−3, respectively. The electrical characteristic and short channel effect i.e. DIBL and subthreshold swing, for different body doping were deliberated. The result also suggests the required change in the pillar design in maintaining the gate channel.

Enhanced performance of vertical double gate MOSFET (VDGM) with oblique rotating implantation (ORI) method

An enhanced performance of vertical double gate MOSFET (VDGM) structure was revealed by adopting the oblique rotating ion implantation (ORI) method. The device structure was simulated based on TCAD tools and verified by good matching data with the published experimental results. With ORI method a symmetrical self-aligned source/drain regions over the silicon pillar and sharp vertical channel profile was observed. With L<inf>g</inf> = 50nm, the V<inf>T</inf> is 0.96V in double gate and increased to 1.2V in single gate structure. The sub threshold swing, S = 81.9 mV/dec and S = 87.7 mV/dec were obtained for double and single gate devices respectively. Similarly, large I<inf>Dsat</inf> = 370µA/µm was observed for double gate compared to single gate device. By scaling the L<inf>g</inf> into 50nm, the V<inf>T</inf> remains almost the same when the L<inf>g</inf> is larger than 80nm. However, it decreases rapidly when scaled down to 50nm. The leakage current increases rapidly when the L<inf>g</inf> is scaled down to 100nm and beyond. However, the ratio of I<inf>ON</inf> – I<inf>OFF</inf> is seen to be increases even with shorter L<inf>g</inf>. These results indicates that ORI method is essential for overcoming various SCE as scaling the channel length down to nanometer regime.

Artificial intelligence techniques for SPICE optimization of MOSFET modeling

This paper proposes new method for optimize and verified electric characterization graph of MOSFET by using artificial neural network. Optimization using Neural Network (ONN) will compare current-voltage (I–V) Characteristic graph between the TCAD simulation and TSPICE modeling as desire data control a model parameter of BSIM. In this paper, the neural network method is dynamic feedforward Neural Network. After NN training, the best result is at Neural Network architecture of 36-30-10-5 with Mean Squared Error (MSE) of 1e-28 at epoch of 5.

Ballistic and high field transport in a nano-MOSFET

The ballistic transport has been extensively discussed for years in search for enhancement of device and circuit performance. The device performance is expected to improve as channel length is reduced below the scattering-limited mean free path (mfp). However, several experimental observations [1–3] reveal that the mobility degrades when the channel length decreases below the long-channel mean free path. Riyadi and Arora[4, 5] point to the fact that ballistic injection from the contacts play a predominant role in enhancing the ballistic mean free path. Non-stationary transient transport results in reduced mobility as transit time delay is below the collision-limited mean free time. Hence steady state is never realized in ballistic devices. The other factor that degrade the mobility is the presence of high electric field E=V/L that is necessarily high in scaled-down channel of length L. So far the applied voltage V is below the critical voltage for triggering nonlinear behavior, the high-field effects are negligible as in the experiments of Robertson and Dumin [2]. It was revealed that a mobility of 25,000 cm2/V.s in a 500-μm channel reduces to only 800 cm2/V.s in a 0.2-μm channel at 4.2 K. High mobilities are thus more susceptible to degradation. The critical voltage Vc∞ and Vc play a predominant role in defining whether or not high-field effects are present. The criteria to unscramble ballistic effects from high-field effects will be presented. Fig. 1 shows the critical voltage in a ballistic as well as long-channel MOSFET. As expected, ballistic effect disappears at longer channel length. Actually high-field effects are suppressed in a ballistic channel. At a low voltage of V=0.1 V, the high-field effects are largely absent at which experimental data is obtained. As applied voltage increases and surpasses the critical voltage, high-field effect further suppresses the mobility. Fig. 2 gives the results of a comparison of theoretical formalism developed with the experimental data. An expression for the ultimate saturation velocity as arising from the intrinsic velocity for a MOSFET is obtained and is critical to interpretation of the experimental data. This intrinsic velocity depends on temperature and carrier concentration. The agreement with the experimental data over a wide range of channel length and ambient temperature gives credence to the theory as well as elucidates new light as new directions are discovered for design and development of low-dimensional devices, including nanowires and carbon-based devices.

Investigation of short channel immunity of fully depleted double gate MOS with vertical structure

The electrical performance of fully depleted double gate MOSFET devices with vertical structure feature were evaluated with the implementation of oblique rotating implantation (ORI) method for several silicon pillar thicknesses using virtual wafer tool. The difference in the subthreshold performance is well noticed, as well as the potentials across the channel for different geometries. The implication of channel length reduction shows that in fully depleted feature, thinner pillar will result in better subthreshold performances than the thicker structure while maintaining the high on-current. As a result, thinner pillar delivers better short channel characteristic control in further channel scaling up to 20 nm.

Reduced parasitic capacitances analysis of nanoscale vertical MOSFET

Quantitative comparison analysis was made between standard vertical MOSFET, vertical MOSFET with FILOX (Fillet Local Oxidation) and vertical MOSFET that combine ORI (Oblique Rotating Implantation) and FILOX technology. Due to a very thin gate oxide separated the gate track and source/drain electrode in standard vertical MOSFET, tremendous increase effects of gate-to-drain and gate-to-source parasitic capacitances was observed. The FILOX device was found to have a lower gate-to-source capacitance compared to FILOX + ORI device due to titled implants used in ORI for self-aligned S/D region formation and SCE control. Thus, thicker oxide on the top and bottom of silicon pillar or so-called FILOX structure has significantly reduce the intrinsic gate capacitance. However, with the addition of titled implants in FILOX + ORI device, the gate-to-drain capacitance has been significantly reduced while has a small difference (10 – 15%) of reducing gate-to-source capacitance as compared to FILOX device. Therefore, the addition of ORI method can suppress the effect of intrinsic gate capacitances and deliberately control the SCE with the self-aligned S/D region onto silicon pillar as scaling the device into nanometer realm.