Steven H. Voldman

Foundation of rf CMOS and SiGe BiCMOS technologies

This paper provides a detailed description of the IBM SiGe BiCMOS and rf CMOS technologies. The technologies provide high-performance SiGe heterojunction bipolar transistors (HBTs) combined with advanced CMOS technology and a variety of passive devices critical for realizing an integrated mixed-signal system-on-a-chip (SoC). The paper reviews the process development and integration methodology, presents the device characteristics, and shows how the development and device selection were geared toward usage in mixed-signal IC development.

Semiconductor process and structural optimization of shallow trench isolation-defined and polysilicon-bound source/drain diodes for ESD networks

The impact of MOSFET source/drain junction scaling on the ESD robustness of shallow trench isolation (STI)-defined diode structures is shown for the first time. ESD robustness improvements to STI-bound p/sup +/ diodes using germanium preamorphization and deep B11 implants, and polysilicon-bordered ESD networks are also discussed.

Analysis of snubber-clamped diode-string mixed voltage interface ESD protection network for advanced microprocessors☆

Abstract A novel snubber-clamped diode-string ESD protection circuit for mixed voltage interface microprocessor applications is described. Analytical models, circuit simulation, electrical characterization, ESD electrothermal simulation, and ESD test data, will be shown for shallow trench isolation (STI) and LOCOS CMOS technologies.

Scaling, optimization and design considerations of electrostatic discharge protection circuits in CMOS technology

Abstract The effect of scaling on electrostatic discharge (ESD) robustness in 1.2 to 0.25 μm channel length CMOS technologies is explored for ESD protection circuits and MOSFET structures. Results show that ESD robustness decreases as ESD structures are scaled to smaller dimensions in future technologies. Technology benchmarking, using a standardized ESD design, for evaluating ESD robustness is discussed. The ESD sensitivity of ESD designs to geometrical and semiconductor process parameters are evaluated. An analytical development for electro-thermal failure is developed based on electro quasi-static and adiabatic assumptions. ESD scaling relationships are developed applying MOSFET constant electric field scaling theory. ESD robustness scales as 1/α 3 2 , where α is the scaling parameter. The scaling relationship derived from the analytical model is then compared to established power-to-failure ESD models. The impact of MOSFET scaling on the ESD robustness of MOSFET structures is then discussed. MOSFET scaling as a function of technology generation shows that snapback breakover and sustaining voltages are decreasing with each technology generation. Optimization, design constraints and technology tradeoffs in CMOS technology development are then shown using a design curve methodology.

ESD protection in a mixed-voltage interface and multirail disconnected power grid environment in 0.50- and 0.25-/spl mu/m channel length CMOS technologies

On-chip ESD protection for semiconductor chips with mixed-voltage interface applications and internal multiple power bus architecture is discussed. ESD robustness in shallow trench isolation 0.50- and 0.25-/spl mu/m channel-length CMOS technologies is demonstrated using novel ESD structures. >

Mixed-voltage interface ESD protection circuits for advanced microprocessors in shallow trench and LOCOS isolation CMOS technologies

Optimization of a 3.3-V/ 5.0-V tolerant electrostatic discharge (ESD) protection network for both diffused n-well/LOCOS and retrograde well/shallow trench isolation (STI) CMOS technologies in a RISC microprocessor is discussed. ESD-related semiconductor-process key design features, ESD circuit operation, data, simulation and failure analysis are presented. ESD robustness of 4000-V human body model (HBM), 400-V machine model (MM), and 1500-V charge device model (CDM) is achieved in both technologies using a common design.<<ETX>>

Latchup in CMOS technology

This paper is a review of the latchup phenomena in past and present CMOS technologies. Both static and transient characterization techniques are described, as well as process related solutions and layout ground rule constraints. Technology scaling implications are discussed in the context of latchup holding voltage/current and minimum N/sup +/ to P/sup +/ spacing.

Analysis of snubber-clamped diode-string mixed voltage interface ESD protection network for advanced microprocessors

A novel snubber-clamped diode-string ESD protection circuit for mixed voltage interface microprocessor applications is described. Analytical models, circuit simulation, electrical characterization, ESD electrothermal simulation, ESD test data, and an ESD analytical failure model are shown for shallow trench isolation (STI) and LOCOS CMOS technologies.

ESD robustness and scaling implications of aluminum and copper interconnects in advanced semiconductor technology

ESD testing results of aluminum and copper interconnect wires and vias for advanced semiconductor technologies demonstrate that interconnects will be a limiting failure mechanism in the future for ESD robustness of semiconductor chips. Comparison of copper and aluminum interconnect and via ESD robustness and failure mechanisms will be shown. Results demonstrate an improvement in the ESD robustness of a Cu-based interconnect system, compared to AI-based interconnects, with an improvement in the critical current, in the human body and machine model time regimes.

Electrostatic discharge characterization of epitaxial-base silicon-germanium heterojunction bipolar transistors

This paper investigates high-current and electrostatic discharge (ESD) phenomena in pseudomorphic epitaxial-base silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) in base-collector, base-emitter, collector-emitter and collector-to-substrate configurations. Transmission line pulse (TLP) and ESD human body model (HBM) wafer-level reliability testing of SiGe HBTs is completed for high-current characterization and evaluation of the ESD robustness of a BiCMOS SiGe technology.