Peter Bendix

ESD-induced internal core device failure: new failure modes in system-on-chip (SOC) designs

With MOSFET scaling, increased design complexity, and multiple system power domains, ESD failures occur in internal core areas which are not connected to external package pins. A review of the various internal core device failure mechanisms and design recommendations are presented.

The effects of substrate coupling on triggering uniformity and ESD failure threshold of fully silicided NMOS transistors

We present a multi-finger turn-on model incorporating substrate coupling effects in multi-finger NMOS transistors during ESD events. It is demonstrated that the substrate coupling enables uniform triggering in a multi-finger structure. In addition, we show that fully silicided transistors can be used successfully as an ESD protection device without any design/process options if the effective epi thickness is larger than 1.5 /spl mu/m or bulk wafer is used.

Investigations of Salicided and Salicide-Blocked MOSFETs for ESD Including ESD Simulation

Standard salicided MOSFETs have been repeatedly shown to have inferior ESD protection properties in comparison to salicide-blocked MOSFETs. Standard explanations typically attribute this to shallower current flow and higher peak current density in salicided devices due to the higher conductivity of salicides. In this work we present a numerical analysis of the phenomenon using physical mixed-mode circuit-device simulation. Our results show that the inherent lack of thickness uniformity known to exist in salicide layers can lead to local concentration of current flow and thus local failure of the device.

Prediction of interconnect adjacency distribution: derivation, validation, and applications

An analytical interconnect adjacency distribution model for random logic interconnect networks based on the Bernoulli probability distribution is derived. By definition, interconnect adjacency is the fractional length of an interconnect for which there is a neighboring interconnect at minimum spacing. Some possible applications of the interconnect adjacency distribution are statistical cross-talk analysis, interconnect yield prediction, and statistical interconnect reference circuit for more realistic capacitance estimation.The model uses only simple and readily available system parameters well known to designers. These are the wire-length distribution and the average channel utilization. Comparison to product data shows good agreement with the model.

Optimization of a 0.13 /spl mu/m CMOS backend interconnect process for ASIC SOC: low K dielectric vs. Cu conductor

A backend optimization scheme for a 0.13 /spl mu/m CMOS process is illustrated based on a set of performance and process metrics. Performance is measured against manufacturing risk and expense with a focus on the requirements for ASIC/SOC. In evaluating how to effectively optimize 0.13 /spl mu/m high performance ASIC/SOC, we compared two technology enhancements-Cu and low K. The results demonstrate that low K is comparable in performance with thickness-scaled Cu but with lower manufacturing risk. Further studies show that placing low-k IMD in the top few layers rather than in all the layers provides the most optimal solution for the 0.13 um ASIC/SOC requirements.

The impact of Cu/low /spl kappa/ on chip performance

A new model to predict percentage of performance improvement using copper and/or low /spl kappa/ is rigorously derived. Based on the new model, it is shown that for a typical ASIC design in 0.25 /spl mu/m technology, using copper interconnect alone can improve the speed by about 10%; however in the same technology, using low /spl kappa/ dielectric (/spl epsi//sub r/=2.5) alone can improve the speed by about 27%. The new model indicates that the performance gain for copper and low /spl kappa/ are not additive. Finally, the model is applied to the NTRS projections to explore the performance gain through future technology generations.