Sarma S. Gunturi

Game theoretic approach to power control in cellular CDMA

In this paper, we present the power control problem in CDMA wireless data networks in the analytical setting of noncooperative game theory. User satisfaction is represented as a net utility function, which is the difference of a strictly concave function, based on signal to interference ratio, and a cost term on users power. A detailed analysis for the existence and uniqueness of Nash equilibrium for the above noncooperative game is presented. Next, a decentralized power control algorithm is developed which converges to the Nash equilibrium, as demonstrated by both analytical and simulation methods. The framework is then extended to the multicell case, making user utilities depend on base-station assignment as well as powers. We propose a generalized algorithm that can handle base station assignment and hand-off, as well as power control, and study by extensive simulations its performance in a dynamic environment.

Quantization noise improvement of Time to Digital converter (TDC) for ADPLL

A number of communication applications are moving to digitally motivated architectures for their radio frequency module. This includes GSM-EDGE, WLAN, Bluetooth, GSM-GPRS, WiMAX. The All Digital PLL(ADPLL) forms the core of this architecture. The objective of the ADPLL is to generate a clean carrier frequency ƒc, based on a input reference frequency ƒref. As part of the phase error measurement of the PLL, a Time to Digital converter(TDC) is used to measure the delay between ƒref clock edge and carrier clocking edge. An inverter chain is used to measure this delay as a integer number of basic inverter delay. This measurement error is termed TDC quantization error and effects the phase noise present in the final carrier. Due to the coarse delay of the basic inverter available, TDC introduces large quantization noise at the output of the PLL. This is too high for systems operating at high carrier frequencies or systems which have a tight phase noise requirement. This paper presents techniques to improve TDC quantization noise.

Mitigation of narrowband interference in differentially modulated communication systems

Integration of RF/Analog and digital into a single chip can result in the coupling of digital spurs in the analog front end of a communication systems and can severely degrade the receiver performance. In this paper, we propose a novel receiver architecture of a notch filter together with the feedback filter (FBF) of the decision feedback equalizer (DFE) to mitigate the impact of narrowband interference in differentially modulated communication systems without enhancing the inter-symbol interference (ISI). The proposed solution can be adapted to receiver architectures that employ either coherent or non-coherent demodulation of differentially modulated systems. Simulation results demonstrating the spur mitigation capability of the proposed solution is presented.

Robust channel estimation for 802.11n (MIMO-OFDM) systems

In a receiver for multiple input multiple output (MIMO) 802.11n system, the residual carrier frequency offset (CFO), after synchronization with training symbols in the preamble of a packet, affects the accuracy of channel estimation. The residual CFO causes inter-carrier interference as well as inter-spatial stream interference. A decision directed algorithm to estimate and correct the residual CFO before channel estimation is presented. A 802.11n packet transmitted with high-throughput mixed mode (HT-MM) packet format has both legacy and high-throughput (HT) training fields. Typically, the channel is estimated only with HT training fields. In this paper, a channel estimation technique which uses both the legacy and high-throughput training field is proposed. Simulation results demonstrating the improvement in channel estimation and packet error rate (PER) performance are also presented.

Principal architectural changes in polar transmitter in DRP design for WLAN

In Digital Radio Processor(DRP) an All-digital Phase Locked Loop(ADPLL) forms the core of the architecture with a digitally controlled oscillator(DCO) being the counterpart of Voltage Controlled Oscillator (VCO) in a conventional PLL design. In addition to this, the RF modulation is also performed digitally by feeding Frequency Control Word(FCW) into the ADPLL. This implies that the DCO should be able to support the frequency range requirements for the modulation technique. DCO modulation range for GSM and Bluetooth systems is few hundreds of KHz. However, in order to support WLAN in both 2.4 GHz (ISM band) and 5–5.9 GHz(UNII) bands the DCO needs to have 1.2 GHz modulation range at 12 GHz frequency. Such a DCO becomes extremely sensitive to supply voltage fluctuations. We propose an algorithm which reduces the modulation range requirement of the DCO and hence its sensitivity to supply voltage. In DRP, the modulated clock output of the ADPLL is used as the sampling clock for the digital logic. For GSM and Bluetooth systems the drift introduced in phase samples by using the modulated clock is negligible. However, for WLAN, merely using the modulated clock for sampling is disastrous as it will introduce intolerable drift in the phase samples when compared to phase samples generated by using a constant uniform clock. We propose a predistortion scheme for frequency control words(FCW) to correct this effect of modulated clock.