Sthanunathan Ramakrishnan

Exploiting signal and noise statistics for fixed point FFT design optimization in OFDM systems

Scaling the different stage outputs in an FFT appropriately is crucial for getting a good Signal to Quantization noise ratio (SQNR) in fixed point FFT design. Traditional designs have either handled this through Convergent block floating point technique (CBFP), which has memory, computation and latency penalties or through time consuming simulations. In this paper, we consider the special case of FFT design for OFDM transceivers. We exploit the Gaussian nature of OFDM signals to predict the bit-growth of the signal through the various stages of the FFT and propose a technique to scale the signal appropriately. Additionally, we investigate the quantization error profile and propose a technique to improve SQNR by exploiting the presence of null tones at the band edges. With the proposed techniques, the performance comes close to the CBFP design, with no increase in complexity compared to existing static designs. Simulation results illustrating the performance improvements of the proposed technique are presented.

Robust floor determination for indoor positioning

In recent years, indoor positioning system using existing Wi-Fi infrastructure and MEMS sensors have received significant attention. A key requirement for a complete 3-dimensional indoor positioning algorithm is to provide an accurate and robust user floor location estimate in a multi-floor building. In this paper, we propose novel techniques to estimate user floor location based on the received radio signal strengths from Wi-Fi access points in the building. We illustrate its performance advantages through simulations and multiple field test results across typical use case scenarios. We further discuss Wi-Fi outage scenarios during which the performance of the Wi-Fi based floor determination algorithm is limited. We then propose a method to blend the Wi-Fi access points based floor estimate with pressure sensor measurements to enhance the overall performance of the algorithm. Finally, we present performance results from field tests to validate the efficacy and robustness of our proposed techniques.

IQ mismatch compensation using time domain signal processing: A practical approach

In recent times, analysis of transceiver RF front-end analog impairments and their compensation using digital signal processing techniques have drawn increasing interest. Analysis and calibration of frequency dependent and frequency independent IQ imbalance (FD-IQI & FI-IQI) are explored in this paper. In order to reduce implementation complexity, we propose sequential compensation rather than joint compensation of FD-IQI and FI-IQI. A low-complexity technique for compensation of FD-IQI in time-domain is presented. Fundamental limit on estimation accuracy of FI-IQI parameters is derived in the presence of uncompensated FD-IQI. Impact of the proposed technique on packet-error-rate (PER) performance of a IEEE 802.11g receiver is demonstrated via silicon measurements.

Parameter mismatch estimation in a parallel interleaved ADC

In this paper we propose a novel method for estimating the gain, DC offset and sample timing mismatches between component ADCs in a Parallel Interleaved ADC. We propose the use of a reference ADC, operating at a lower rate, that precludes the need for any calibration period. The reference ADC is clocked using a novel scheme to provide reference samples that are used by the estimation algorithm We propose the use of Least Squares (LS) based approach for correcting the gain and DC offset mismatches as well as a bisection search and a fixed step adaptation for estimating/correcting the sample timing offset. These algorithms ensure fast initial convergence and good steady state tracking with little implementation overhead. Simulation results are presented to illustrate the efficacy of these techniques.

Magnetic structure of Co(Cr0.925Fe0.075)2O4

We report results of neutron diffraction (ND) measurements on Co(Cr0.925Fe0.075)2O4 compound and determination of its magnetic structure. ND data at 90 K shows ferrimagnetic structure which is consistent with the bulk magnetization transition temperature, TC (~ 120 K). Appearance of additional peaks at 20 K coincides with the view that a magnetostructural transition occurs at TS (~ 26 K) in bulk magnetization of the sample.

Principal architectural changes in polar transmitter in DRP design for WLAN

In Digital Radio Processor(DRP) an All-digital Phase Locked Loop(ADPLL) forms the core of the architecture with a digitally controlled oscillator(DCO) being the counterpart of Voltage Controlled Oscillator (VCO) in a conventional PLL design. In addition to this, the RF modulation is also performed digitally by feeding Frequency Control Word(FCW) into the ADPLL. This implies that the DCO should be able to support the frequency range requirements for the modulation technique. DCO modulation range for GSM and Bluetooth systems is few hundreds of KHz. However, in order to support WLAN in both 2.4 GHz (ISM band) and 5–5.9 GHz(UNII) bands the DCO needs to have 1.2 GHz modulation range at 12 GHz frequency. Such a DCO becomes extremely sensitive to supply voltage fluctuations. We propose an algorithm which reduces the modulation range requirement of the DCO and hence its sensitivity to supply voltage. In DRP, the modulated clock output of the ADPLL is used as the sampling clock for the digital logic. For GSM and Bluetooth systems the drift introduced in phase samples by using the modulated clock is negligible. However, for WLAN, merely using the modulated clock for sampling is disastrous as it will introduce intolerable drift in the phase samples when compared to phase samples generated by using a constant uniform clock. We propose a predistortion scheme for frequency control words(FCW) to correct this effect of modulated clock.