Jay S. Burnham

The combined effects of deuterium anneals and deuterated barrier-nitride processing on hot-electron degradation in MOSFET's

This paper describes the combined effects of deuterium anneals and deuterated barrier-nitride processing on hot-electron degradation in MOSFETs. Devices subjected to a 60-min, 400/spl deg/C, 10% deuterium/90% nitrogen anneal after silicidization show a 32/spl times/ improvement in hot-electron lifetime. These same devices are then passivated with a deuterated barrier-nitride layer formed using deuterated ammonia (ND/sub 3/) and conventional silane (SiH/sub 4/). Further deuterium anneals along with conventional contact and metal-level processes are used to integrate the devices. Hot-electron stressing and SIMS analysis performed at various points in the processing give insight to methods of retaining the beneficial effects of deuterium during subsequent thermal processing.

Nitrided gate oxides for 3.3-V logic application: reliability and device design considerations

Device characteristics and reliability in a 3.3-V logic CMOS technology with various gate oxidation and nitridation processes are described. The technology was designed to extend 3.3-V devices to the ultimate dielectric reliability limit while maintaining strict manufacturing cost control. A nitrided gate oxide provided the means to maintain hot-electron reliability at the level of the previous iteration, but at higher performance and lower processing cost. Conventional furnace processes in nitrous and nitric oxide, high-pressure oxidation in oxygen and nitrous oxide, and rapid-thermal processes using nitrous and nitric oxide were investigated. We found that the concomitant variations in fixed charge and thermal budget have a significant influence on both n-FET and p-FET device parameters such as threshold voltage, carrier mobility, and inverse short-channel effect (ISCE). Reliability effects, such as charge to breakdown (QBD), hot-electron degradation, and negative-bias temperature instability (NBTI) were examined and correlated with the nitrogen profile in the gate dielectric. Secondary ion mass spectroscopy (SIMS) profiles were used to characterize the oxidation techniques and to correlate gate dielectric composition to the parametric and reliability parameters.

Negative bias temperature instability on three oxide thicknesses (1.4/2.2/5.2 nm) with nitridation variations and deuteration

Abstract In these experiments, we explored various methods of nitridation of thermal oxide. Rapid thermal oxidation (RTO), rapid thermal oxidation with nitric oxide (RTNO), remote plasma nitridation (RPN), and decoupled plasma nitridation (DPN) processes were performed, and the result on 1.4, 2.2, and 5.2 nm oxides was measured. It is shown that the initial threshold voltage and the shift during negative bias temperature instability (NBTI) stress are proportional to the nitrogen in the oxide. Not surprisingly the threshold voltage is dependent on the interfacial nitrogen, but it was also found that the NBTI shift depends on the total nitrogen incorporated throughout the bulk of the insulator. The thinnest oxide showed boron penetration for the unnitrided split, but also very low NBTI shift. Furthermore, wafers from each of the aforementioned nitridation variants were processed with and without deuterium passivation. Although the NFET hot–carrier response is substantially improved, no significant advantage in NBTI shift is observed.

Advanced metal and dielectric barrier cap films for Cu low k interconnects

Multi-layer SiN barrier film with high breakdown and low leakage is developed for Cu low k interconnects and is compared with the SiCNH barrier film used at previous technology nodes. Ultra-thin SiN barrier cap film also provides high conformality and fills recess in Cu lines observed post CMP. A significant enhancement in electro migration (EM) performance was obtained by selectively depositing Co on top of Cu lines followed by conformal multi-layer SiN barrier film. Further EM lifetime improvement is obtained by using a Co liner to form a wrap around structure with completely encapsulated Cu. An integrated in-situ preclean/ metal/dielectric cap chamber was used to avoid any oxidation of Cu/Co layers. Kinetic studies of CVD Co liner/Co cap samples show significant increase in EM activation energy (1.7 eV) over samples with dielectric only barrier film (0.9-1 eV). The complete wrap around structure with Co liner and Co cap shows improved device reliability.

Sulfur-free cleaning strategy for advanced mask manufacturing

Existing cleaning technology using sulfuric acid based chemistry has served the mask industry quite well over the years. However, the existence of residue on mask surfaces is becoming more and more of a problem at the high energy wavelengths used in lithography tool for wafer manufacturing. This is evident by the emergence of sub-pellicle defect growth and backside hazing issues. A large source of residual contamination on the surface of masks is from the mask manufacturing process, particularly the cleaning portion involving sulfuric acid. Cleaning strategies can be developed that eliminate the use of sulfuric acid in the cleaning process for advanced photomasks and alternative processes can be used for cleaning masks at various stages of the manufacturing process. Implementation of these new technologies into manufacturing will be discussed as will the resulting improvements, advantages, and disadvantages over pre-existing mask cleaning processes.

Diffusion and Defect Structure in Nitrogen Implanted Silicon

Nitrogen diffusion and defect structure were investigated after medium to high dose nitrogen implantation and anneal. 11 keV N 2 + was implanted into silicon at doses ranging from 2×10 14 to 2×10 15 cm −2 . The samples were annealed with an RTA system from 750°C to 900°C in a nitrogen atmosphere or at 1000°C in an oxidizing ambient. Nitrogen profiles were obtained by SIMS, and cross-section TEM was done on selected samples. TOF-SIMS was carried out in the oxidized samples. For lower doses, most of the nitrogen diffuses out of silicon into the silicon/oxide interface as expected. For the highest dose, a significant portion of the nitrogen still remains in silicon even after the highest thermal budget. This is attributed to the finite capacity of the silicon/oxide interface to trap nitrogen. When the interface gets saturated by nitrogen atoms, nitrogen in silicon can not escape into the interface. Implant doses above 7×10 14 create continuous amorphous layers from the surface. For the 2×10 15 case, there is residual amorphous silicon at the surface even after a 750°C 2 min anneal. After the 900°C 2 min anneal, the silicon fully recrystallizes leaving behind stacking faults at the surface and residual end of range damage.

Reliability of Cu Interconnects with Ta Implant

In this study, a novel method is explored for improving the electromigration lifetime of Cu wires, using a blanket Ta implantation into both the oxide and Cu on the surface of a wafer. For the highest implant dose, the electromigration lifetime is improved by over 5X using this method, with a minimal increase in wire resistance. An increase in lifetime is achieved, even for an average surface concentration of Ta on the order of 0.1 atm%. The line-to-line leakage at high voltages (> 5 V) increases with the Ta implant, with higher leakage at higher Ta concentrations. The lifetime for time dependent dielectric breakdown (TDDB) is significantly degraded for high Ta doses, but not for lower Ta doses, suggesting that there may be a window for improving electromigration lifetime while maintaining high dielectric reliability.

Wavelength-dependent spot defects on advanced embedded attenuated phase-shift masks

At the challenging ground rules required for 90 nm and 65 nm photomask production, new types of photomask defects are becoming increasingly prevalent. This paper discusses one particular new defect type found on critical 90 nm embedded attenuated phase-shift masks (EAPSMs). These defects had varying transmission characteristics depending on the wavelength used for analysis. Given that photomask inspection wavelength has historically lagged behind lithography wavelength, this type of defect can go undetected and poses a grave risk to wafer lithography yield. Detection and characterization methodologies will be presented along with aerial image analysis and wafer print evaluation results.

The effect of fluorine in an advanced CMOS process with triple (1.6/2.2/5.2 nm) nitrided gate oxide

Fluorine is introduced into the PFET and NFET of a triple-oxide (1.6/2.2/5.2 nm) 90 nm nitrided-oxide CMOS technology. While the effects on the PFET gate oxide are relatively subtle, the NFET is very significantly affected. The effective thickness of the oxide increases by 0.5 nm, much of the nitrogen is removed, and the structural integrity of the film is compromised. Electrical data, SIMS, TEM, and HRTEM analysis are used to characterize the films.

Improved Electromigration Lifetime for Copper Interconnects using Tantalum Implant

In this study, a novel method is explored for improving the electromigration lifetime of Cu wires, using Ta implantation into Cu. For high implant doses (2E15 cm −2 ), the electromigration lifetime is improved by over 5X using this method. An increase in lifetime is achieved, even for an average surface concentration of Ta on the order of 0.1 atm%. We propose that the improvement in electromigration lifetime is due to the reduction of defects at the SiN/Cu interface due to the presence of Ta. The line-to-line leakage at high voltages (> 5V) increases with the Ta implant, with higher leakage at higher Ta concentrations, so the Ta dose must be limited to avoid excessive leakage.