Terence B. Hook

Lateral ion implant straggle and mask proximity effect

Lateral scattering of retrograde well implants is shown to have an effect on the threshold voltage of nearby devices. The threshold voltage of both NMOSFETs and PMOSFETs increases in magnitude for conventional retrograde wells, but for triple-well isolated NMOSFETs the threshold voltage decreases for narrow devices near the edge of the well. Electrical data, SIMS, and SUPREM4 simulations are shown that elucidate the phenomenon.

The effects of fluorine on parametrics and reliability in a 0.18-/spl mu/m 3.5/6.8 nm dual gate oxide CMOS technology

Fluorine was introduced into the gate oxide by implantation at various doses into the gate polysilicon. After complete processing, the fluorine remaining in the system was characterized by secondary ion mass spectroscopy (SIMS) and then correlated to a number of important technological device parameters. The threshold voltages of thin (3.5 nm) and thick (6.8 nm) field-effect transistors (FETs) were measured, and an increase in interface trap density with increasing fluorine content was identified. An increase in oxide thickness and improvement in hot-carrier immunity were observed. Little change to oxide dielectric integrity was noted, but the negative bias threshold instability (NBTI) shift was improved with the introduction of fluorine. These data indicate that benefits may be obtained by introducing fluorine into the p-type FET (PFET), but that the increase in interface traps makes fluorine in the n-type FET (NFET) less attractive from a technological perspective. These data are in agreement with a previously proposed mechanism whereby fluorine removes hydrogen-related sites from the oxide.

High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering

A leading edge 90 nm logic bulk foundry technology with 45 nm gate length devices, incorporating strain engineering, is described in this paper. Gate length and dielectric scaling, along with optimized strain engineering, enable high performance devices, which are amongst the best reported to date. Short channel effect control down to 35 nm is demonstrated. Both NMOS and PMOS performance are improved through careful optimization of stress effects from both trench isolation and contact etch stop nitride film. Furthermore, analysis of the channel mobility and current enhancement is used to gain understanding of the stress mechanisms, and hence layout design practice should be optimized for performance.

Enchanced multi-threshold (MTCMOS) circuits using variable well bias

Advanced CMOS technology can enable high levels of performance with reduced active power at the expense of increased standby leakage, MTCMOS has previously been described as a method of reducing leakage in standby modes, by addition of a power supply interrupt switch. Enhancements using variable well bias and layout techniques are described and demonstrate increased performance and reduced leakage over conventional MTCMOS circuits.

Ultralow-power SRAM technology

An ultralow-standby-power technology has been developed in both 0.18-µm and 0.13-µm lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage six-transistor (6T) SRAM cell sizes are 4.81 µm2 and 2.34 µm2, corresponding respectively to the 0.18-µm and 0.13-µm design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25°C and is less than 400 fA per cell at 1.5 V, 85°C. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the well-known gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.

Mechanism of Threshold Voltage Shift (ΔVth) Caused by Negative Bias Temperature Instability (NBTI) in Deep Submicron pMOSFETs

The physical mechanism responsible for negative bias temperature instability (NBTI), which is basic to the minimization of this degradation mode, is investigated, and an analytical model is developed accordingly. Experiments with 1.7 nm to 3.3 nm gate dielectrics fabricated by different processes demonstrate the capability of the proposed model.

The combined effects of deuterium anneals and deuterated barrier-nitride processing on hot-electron degradation in MOSFET's

This paper describes the combined effects of deuterium anneals and deuterated barrier-nitride processing on hot-electron degradation in MOSFETs. Devices subjected to a 60-min, 400/spl deg/C, 10% deuterium/90% nitrogen anneal after silicidization show a 32/spl times/ improvement in hot-electron lifetime. These same devices are then passivated with a deuterated barrier-nitride layer formed using deuterated ammonia (ND/sub 3/) and conventional silane (SiH/sub 4/). Further deuterium anneals along with conventional contact and metal-level processes are used to integrate the devices. Hot-electron stressing and SIMS analysis performed at various points in the processing give insight to methods of retaining the beneficial effects of deuterium during subsequent thermal processing.

UTBB FDSOI transistors with dual STI for a multi-V t strategy at 20nm node and below

We introduce an innovative dual-depth shallow trench isolation (dual STI) scheme for Ultra Thin Body and BOX (UTBB) FDSOI architecture. Since in the dual STI configuration wells are isolated from one another by the deepest trenches, this architecture enables a full use of the back bias while staying compatible with both standard bulk design and conventional SOI substrates. We demonstrate in 20nm ground rules that we are able to tune Vt by more than 400mV, that transistor performance can be boosted by up to 30% and that Ioff can be controlled over 3 decades by allowing more than VDD/2 to be applied on the back gate.

Analysis and Modeling of Threshold Voltage Mismatch for CMOS at 65 nm and Beyond

This letter investigates random dopant fluctuation transistor mismatch. The dominance of the halo implant is demonstrated experimentally and with simulation, and a compact model form is developed for improved representation of the phenomenon.

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.