Steven M. Shank

A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications

The first sub-100nm technology that allows the monolithic integration of optical modulators and germanium photodetectors as features into a current 90nm base high-performance logic technology node is demonstrated. The resulting 90nm CMOS-integrated Nano-Photonics technology node is optimized for analog functionality to yield power-efficient single-die multichannel wavelength-mulitplexed 25Gbps transceivers.

Monolithic Silicon Integration of Scaled Photonic Switch Fabrics, CMOS Logic, and Device Driver Circuits

We demonstrate 4 × 4 and 8 × 8 switch fabrics in multistage topologies based on 2 × 2 Mach-Zehnder interferometer switching elements. These fabrics are integrated onto a single chip with digital CMOS logic, device drivers, thermo-optic phase tuners, and electro-optic phase modulators using IBMs 90 nm silicon integrated nanophotonics technology. We show that the various switch-and-driver systems are capable of delivering nanosecond-scale reconfiguration times, low crosstalk, compact footprints, low power dissipations, and broad spectral bandwidths. Moreover, we validate the dynamic reconfigurability of the switch fabric changing the state of the fabric using time slots with sub-100-ns durations. We further verify the integrity of high-speed data transfers under such dynamic operation. This chip-scale switching system technology may provide a compelling solution to replace some routing functionality currently implemented as bandwidth- and power-limited electronic switch chips in high-performance computing systems.

Cascaded Mach-Zehnder wavelength filters in silicon photonics for low loss and flat pass-band WDM (de-)multiplexing.

We present 1-to-8 wavelength (de-)multiplexer devices based on a binary tree of cascaded Mach-Zehnder-like lattice filters, and manufactured using a 90 nm CMOS-integrated silicon photonics technology. We demonstrate that these devices combine a flat pass-band over more than 50% of the channel spacing with low insertion loss of less than 1.6 dB, and have a small device size of approximately 500 × 400 µm. This makes this type of filters well suited for application as WDM (de-)multiplexer in silicon photonics transceivers for optical data communication in large scale computer systems.

A 25 Gbps silicon microring modulator based on an interleaved junction.

A silicon microring modulator utilizing an interleaved p-n junction phase shifter with a V(π)L of 0.76 V-cm and a minimum off-resonance insertion loss of less than 0.2 dB is demonstrated. The modulator operates at 25 Gbps at a drive voltage of 1.6 V and 2-3 dB excess optical insertion loss, conditions which correspond to a power consumption of 471 fJ/bit. Eye diagrams are characterized at up to 40 Gbps, and transmission is demonstrated across more than 10 km of single-mode fiber with minimal signal degradation.

Coupling modulation of microrings at rates beyond the linewidth limit

We demonstrate optical modulation rates exceeding the conventional cavity linewidth limit using a silicon coupling modulated microring. Small-signal measurements show coupling modulation was free of the parasitic cavity linewidth limitations at rates at least 6× the cavity linewidth. Eye diagram measurements show coupling modulation achieved data rates > 2× the rate attainable by conventional intracavity phase modulation. We propose to use DC-balanced encoding to mitigate the inter-symbol interference in coupling modulation. Analysis shows that coupling modulation can be more efficient than intracavity modulation for large output swings and high-Q resonators. Coupling modulation enables very high-Q resonant modulators to be simultaneously low-power and high-speed, features which are mutually incompatible in typical resonant modulators studied to date.

High-speed receiver based on waveguide germanium photodetector wire-bonded to 90nm SOI CMOS amplifier

The performance of a receiver based on a CMOS amplifier circuit designed with 90nm ground rules wire-bonded to a waveguide germanium photodetector is characterized at data rates up to 40Gbps. Both chips were fabricated through the IBM Silicon CMOS Integrated Nanophotonics process on specialty photonics-enabled SOI wafers. At the data rate of 28Gbps which is relevant to the new generation of optical interconnects, a sensitivity of -7.3dBm average optical power is demonstrated with 3.4pJ/bit power-efficiency and 0.6UI horizontal eye opening at a bit-error-rate of 10(-12). The receiver operates error-free (bit-error-rate < 10(-12)) up to 40Gbps with optimized power supply settings demonstrating an energy efficiency of 1.4pJ/bit and 4pJ/bit at data rates of 32Gbps and 40Gbps, respectively, with an average optical power of -0.8dBm.

Demonstration of electrooptic modulation at 2165nm using a silicon Mach-Zehnder interferometer

We demonstrate electrooptic modulation at a wavelength of 2165nm, using a free-carrier injection-based silicon Mach-Zehnder modulator. The modulator has a V(π)∙L figure of merit of 0.12V∙mm, and an extinction ratio of -23dB. Optical modulation experiments are performed at bitrates up to 3Gbps. Our results illustrate that optical modulator design methodologies previously developed for telecom-band devices can be successfully applied to produce high-performance devices for a silicon nanophotonic mid-infrared integrated circuit platform.

Demonstration of a High Extinction Ratio Monolithic CMOS Integrated Nanophotonic Transmitter and 16 Gb/s Optical Link

We present a 16-Gb/s transmitter composed of a stacked voltage-mode CMOS driver and periodic-loaded reverse biased pn junction Mach-Zehnder modulator. The transmitter shows 9-dB extinction ratio and 10.3-pJ/bit power consumption and operates with 1.3 μm light. Penalties as low as 0.5 dB were seen as compared to a 25-Gb/s LiNbO3 transmitter with both a monolithic metal-semiconductor-metal receiver and a reference receiver at 16-Gb/s operation. We also present an analytic expression for relative transmitter penalty (RTP), which allows one to quickly assess the system impact of design parameters such as peak-to-peak modulator drive voltage, modulator figure of merit, and transmitter extinction ratio to determine the circumstances under which a stacked CMOS cascode driver is desirable.

Monolithically integrated silicon nanophotonics receiver in 90nm CMOS technology node

A monolithically-integrated germanium receiver is fabricated in the IBMs newly established 90nm CMOS-integrated nanophotonics technology node. Technology is promising for cost-effective 10Gbps to 28Gbps optical communications links operating within extended temperature range up to 95°C.

Four- and eight-port photonic switches monolithically integrated with digital CMOS logic and driver circuits

We demonstrate in a single chip a complete multiport photonic switching system using IBM 90-nm photonics-enabled CMOS. The system includes CMOS logic, switch drivers, multistage 4×4 and 8×8 photonic switch fabrics, and thermo-optic phase tuners.